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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jmonkman@adventnetworks.com>
12 *
13 * (C) Copyright 2001
14 * Advent Networks, Inc. <http://www.adventnetworks.com>
15 * Oliver Brown <obrown@adventnetworks.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36/*********************************************************************/
37/* DESCRIPTION:
38 * This file contains the board configuartion for the GW8260 board.
39 *
40 * MODULE DEPENDENCY:
41 * None
42 *
43 * RESTRICTIONS/LIMITATIONS:
44 * None
45 *
46 * Copyright (c) 2001, Advent Networks, Inc.
47 */
48/*********************************************************************/
49
50#ifndef __CONFIG_H
51#define __CONFIG_H
52
53/* Enable debug prints */
wdenkfe8c2802002-11-03 00:38:21 +000054#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
55
56/* What is the oscillator's (UX2) frequency in Hz? */
57#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
58
59/*-----------------------------------------------------------------------
60 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
61 *-----------------------------------------------------------------------
62 * What should MODCK_H be? It is dependent on the oscillator
63 * frequency, MODCK[1-3], and desired CPM and core frequencies.
64 * Here are some example values (all frequencies are in MHz):
65 *
66 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
67 * ------- ---------- --- --- ---- ----- ----- -----
68 * 0x5 0x5 66 133 133 Open Close Open
69 * 0x5 0x6 66 133 166 Open Open Close
70 * 0x5 0x7 66 133 200 Open Open Open
71 * 0x6 0x0 66 133 233 Close Close Close
72 * 0x6 0x1 66 133 266 Close Close Open
73 * 0x6 0x2 66 133 300 Close Open Close
74 */
75#define CFG_SBC_MODCK_H 0x05
76
77/* Define this if you want to boot from 0x00000100. If you don't define
78 * this, you will need to program the bootloader to 0xfff00000, and
79 * get the hardware reset config words at 0xfe000000. The simplest
80 * way to do that is to program the bootloader at both addresses.
81 * It is suggested that you just let U-Boot live at 0x00000000.
82 */
83#define CFG_SBC_BOOT_LOW 1
84
85/* What should the base address of the main FLASH be and how big is
86 * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
87 * The main FLASH is whichever is connected to *CS0. U-Boot expects
88 * this to be the SIMM.
89 */
90#define CFG_FLASH0_BASE 0x40000000
91#define CFG_FLASH0_SIZE 8
92
93/* Define CFG_FLASH_CHECKSUM to enable flash checksum during boot.
94 * Note: the 'flashchecksum' environment variable must also be set to 'y'.
95 */
96#define CFG_FLASH_CHECKSUM
97
98/* What should be the base address of SDRAM DIMM and how big is
99 * it (in Mbytes)?
100 */
101#define CFG_SDRAM0_BASE 0x00000000
102#define CFG_SDRAM0_SIZE 64
103
104/*
105 * DRAM tests
106 * CFG_DRAM_TEST - enables the following tests.
107 *
108 * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
109 * Environment variable 'test_dram_data' must be
110 * set to 'y'.
111 * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
112 * addressable. Environment variable
113 * 'test_dram_address' must be set to 'y'.
114 * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
115 * This test takes about 6 minutes to test 64 MB.
116 * Environment variable 'test_dram_walk' must be
117 * set to 'y'.
118 */
119#define CFG_DRAM_TEST
120#if defined(CFG_DRAM_TEST)
121#define CFG_DRAM_TEST_DATA
122#define CFG_DRAM_TEST_ADDRESS
123#define CFG_DRAM_TEST_WALK
124#endif /* CFG_DRAM_TEST */
125
126/*
127 * GW8260 with 16 MB DIMM:
128 *
129 * 0x0000 0000 Exception Vector code, 8k
130 * :
131 * 0x0000 1FFF
132 * 0x0000 2000 Free for Application Use
133 * :
134 * :
135 *
136 * :
137 * :
138 * 0x00F5 FF30 Monitor Stack (Growing downward)
139 * Monitor Stack Buffer (0x80)
140 * 0x00F5 FFB0 Board Info Data
141 * 0x00F6 0000 Malloc Arena
142 * : CFG_ENV_SECT_SIZE, 256k
143 * : CFG_MALLOC_LEN, 128k
144 * 0x00FC 0000 RAM Copy of Monitor Code
145 * : CFG_MONITOR_LEN, 256k
146 * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
147 */
148
149/*
150 * GW8260 with 64 MB DIMM:
151 *
152 * 0x0000 0000 Exception Vector code, 8k
153 * :
154 * 0x0000 1FFF
155 * 0x0000 2000 Free for Application Use
156 * :
157 * :
158 *
159 * :
160 * :
161 * 0x03F5 FF30 Monitor Stack (Growing downward)
162 * Monitor Stack Buffer (0x80)
163 * 0x03F5 FFB0 Board Info Data
164 * 0x03F6 0000 Malloc Arena
165 * : CFG_ENV_SECT_SIZE, 256k
166 * : CFG_MALLOC_LEN, 128k
167 * 0x03FC 0000 RAM Copy of Monitor Code
168 * : CFG_MONITOR_LEN, 256k
169 * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
170 */
171
172
173/*
174 * select serial console configuration
175 *
176 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
177 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
178 * for SCC).
179 *
180 * if CONFIG_CONS_NONE is defined, then the serial console routines must
181 * defined elsewhere.
182 */
183#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
184#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
185#undef CONFIG_CONS_NONE /* define if console on neither */
186#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
187
188/*
189 * select ethernet configuration
190 *
191 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
192 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
193 * for FCC)
194 *
195 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500196 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkfe8c2802002-11-03 00:38:21 +0000197 */
198
199#undef CONFIG_ETHER_ON_SCC
200#define CONFIG_ETHER_ON_FCC
201#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
202
203#ifdef CONFIG_ETHER_ON_SCC
204#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
205#endif /* CONFIG_ETHER_ON_SCC */
206
207#ifdef CONFIG_ETHER_ON_FCC
208#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
209#define CONFIG_MII /* MII PHY management */
210#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
211/*
212 * Port pins used for bit-banged MII communictions (if applicable).
213 */
214#define MDIO_PORT 2 /* Port C */
215#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
216#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
217#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
218
219#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
wdenk8bde7f72003-06-27 21:31:46 +0000220 else iop->pdat &= ~0x00400000
wdenkfe8c2802002-11-03 00:38:21 +0000221
222#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
wdenk8bde7f72003-06-27 21:31:46 +0000223 else iop->pdat &= ~0x00200000
wdenkfe8c2802002-11-03 00:38:21 +0000224
225#define MIIDELAY udelay(1)
226#endif /* CONFIG_ETHER_ON_FCC */
227
228#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
229
230/*
231 * - Rx-CLK is CLK13
232 * - Tx-CLK is CLK14
233 * - Select bus for bd/buffers (see 28-13)
234 * - Enable Full Duplex in FSMR
235 */
236# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
237# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
238# define CFG_CPMFCR_RAMTYPE 0
239# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
240
241#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
242
243/*
244 * - Rx-CLK is CLK15
245 * - Tx-CLK is CLK16
246 * - Select bus for bd/buffers (see 28-13)
247 * - Enable Full Duplex in FSMR
248 */
249# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
250# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
251# define CFG_CPMFCR_RAMTYPE 0
252# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
253
254#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
255
256/* Define this to reserve an entire FLASH sector (256 KB) for
257 * environment variables. Otherwise, the environment will be
258 * put in the same sector as U-Boot, and changing variables
259 * will erase U-Boot temporarily
260 */
261#define CFG_ENV_IN_OWN_SECT
262
263/* Define to allow the user to overwrite serial and ethaddr */
264#define CONFIG_ENV_OVERWRITE
265
266/* What should the console's baud rate be? */
267#define CONFIG_BAUDRATE 115200
268
269/* Ethernet MAC address - This is set to all zeros to force an
270 * an error if we use BOOTP without setting
271 * the MAC address
272 */
273#define CONFIG_ETHADDR 00:00:00:00:00:00
274
275/* Set to a positive value to delay for running BOOTCOMMAND */
276#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
277
278/* Be selective on what keys can delay or stop the autoboot process
279 * To stop use: " "
280 */
281#define CONFIG_AUTOBOOT_KEYED
282#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
283#define CONFIG_AUTOBOOT_STOP_STR " "
284#undef CONFIG_AUTOBOOT_DELAY_STR
285#define DEBUG_BOOTKEYS 0
286
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500287/*
288 * BOOTP options
wdenkfe8c2802002-11-03 00:38:21 +0000289 */
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500290#define CONFIG_BOOTP_SUBNETMASK
291#define CONFIG_BOOTP_GATEWAY
292#define CONFIG_BOOTP_HOSTNAME
293#define CONFIG_BOOTP_BOOTPATH
294
295#define CONFIG_BOOTP_BOOTFILESIZE
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200296#define CONFIG_BOOTP_DNS
wdenkfe8c2802002-11-03 00:38:21 +0000297
298/* undef this to save memory */
299#define CFG_LONGHELP
300
301/* Monitor Command Prompt */
302#define CFG_PROMPT "=> "
303
Jon Loeliger72eb0ef2007-07-04 22:32:19 -0500304
305/*
306 * Command line configuration.
307 */
308#include <config_cmd_default.h>
309
310#define CONFIG_CMD_BEDBUG
311#define CONFIG_CMD_ELF
312#define CONFIG_CMD_ASKENV
313#define CONFIG_CMD_REGINFO
314#define CONFIG_CMD_IMMAP
315#define CONFIG_CMD_MII
316
317#undef CONFIG_CMD_KGDB
318
wdenkfe8c2802002-11-03 00:38:21 +0000319
320/* Where do the internal registers live? */
321#define CFG_IMMR 0xf0000000
322
323/* Use the HUSH parser */
324#define CFG_HUSH_PARSER
325#ifdef CFG_HUSH_PARSER
326#define CFG_PROMPT_HUSH_PS2 "> "
327#endif
328
329/* What is the address of IO controller */
330#define CFG_IO_BASE 0xe0000000
331
332/*****************************************************************************
333 *
334 * You should not have to modify any of the following settings
335 *
336 *****************************************************************************/
337
338#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
339#define CONFIG_GW8260 1 /* on an GW8260 Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500340#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkfe8c2802002-11-03 00:38:21 +0000341
wdenkfe8c2802002-11-03 00:38:21 +0000342/*
343 * Miscellaneous configurable options
344 */
Jon Loeliger72eb0ef2007-07-04 22:32:19 -0500345#if defined(CONFIG_CMD_KGDB)
wdenkfe8c2802002-11-03 00:38:21 +0000346# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
347#else
348# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
349#endif
350
351/* Print Buffer Size */
352#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
353
354#define CFG_MAXARGS 8 /* max number of command args */
355
356#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
357
358/* Convert clocks to MHZ when passing board info to kernel.
359 * This must be defined for eariler 2.4 kernels (~2.4.4).
360 */
361#define CONFIG_CLOCKS_IN_MHZ
362
363#define CFG_LOAD_ADDR 0x100000 /* default load address */
364#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
365
366
367/* memtest works from the end of the exception vector table
368 * to the end of the DRAM less monitor and malloc area
369 */
370#define CFG_MEMTEST_START 0x2000
371
372#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
373
374#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
wdenk8bde7f72003-06-27 21:31:46 +0000375 + CFG_MALLOC_LEN \
376 + CFG_ENV_SECT_SIZE \
377 + CFG_STACK_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000378
379#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
wdenk8bde7f72003-06-27 21:31:46 +0000380 - CFG_MEM_END_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000381
382/* valid baudrates */
383#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
384
385/*
386 * Low Level Configuration Settings
387 * (address mappings, register initial values, etc.)
388 * You should know what you are doing if you make changes here.
389 */
390
391#define CFG_FLASH_BASE CFG_FLASH0_BASE
392#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
393#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
394#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
395
396/*-----------------------------------------------------------------------
397 * Hard Reset Configuration Words
398 */
399#if defined(CFG_SBC_BOOT_LOW)
400# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
401#else
402# define CFG_SBC_HRCW_BOOT_FLAGS (0)
403#endif /* defined(CFG_SBC_BOOT_LOW) */
404
405/* get the HRCW ISB field from CFG_IMMR */
406#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
wdenk8bde7f72003-06-27 21:31:46 +0000407 ((CFG_IMMR & 0x01000000) >> 7) | \
408 ((CFG_IMMR & 0x00100000) >> 4) )
wdenkfe8c2802002-11-03 00:38:21 +0000409
410#define CFG_HRCW_MASTER ( HRCW_BPS11 | \
wdenk8bde7f72003-06-27 21:31:46 +0000411 HRCW_DPPC11 | \
412 CFG_SBC_HRCW_IMMR | \
413 HRCW_MMR00 | \
414 HRCW_LBPC11 | \
415 HRCW_APPC10 | \
416 HRCW_CS10PC00 | \
417 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
418 CFG_SBC_HRCW_BOOT_FLAGS )
wdenkfe8c2802002-11-03 00:38:21 +0000419
420/* no slaves */
421#define CFG_HRCW_SLAVE1 0
422#define CFG_HRCW_SLAVE2 0
423#define CFG_HRCW_SLAVE3 0
424#define CFG_HRCW_SLAVE4 0
425#define CFG_HRCW_SLAVE5 0
426#define CFG_HRCW_SLAVE6 0
427#define CFG_HRCW_SLAVE7 0
428
429/*-----------------------------------------------------------------------
430 * Definitions for initial stack pointer and data area (in DPRAM)
431 */
432#define CFG_INIT_RAM_ADDR CFG_IMMR
433#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
434#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
435#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
436#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
437
438/*-----------------------------------------------------------------------
439 * Start addresses for the final memory configuration
440 * (Set up by the startup code)
441 * Please note that CFG_SDRAM_BASE _must_ start at 0
442 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
443 */
444#define CFG_MONITOR_BASE CFG_FLASH0_BASE
445
446#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
447#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
448
449/*
450 * For booting Linux, the board info and command line data
451 * have to be in the first 8 MB of memory, since this is
452 * the maximum mapped by the Linux kernel during initialization.
453 */
454#define CFG_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */
455
456/*-----------------------------------------------------------------------
457 * FLASH and environment organization
458 */
459#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
460#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
461
462#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
463#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
464
465#define CFG_ENV_IS_IN_FLASH 1
466
467#ifdef CFG_ENV_IN_OWN_SECT
468# define CFG_ENV_ADDR (CFG_MONITOR_BASE + (256 * 1024))
469# define CFG_ENV_SECT_SIZE (256 * 1024)
470#else
471# define CFG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */
472# define CFG_ENV_ADD ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) - CFG_ENV_SIZE)
473# define CFG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */
474#endif /* CFG_ENV_IN_OWN_SECT */
475
476/*-----------------------------------------------------------------------
477 * Cache Configuration
478 */
479#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
480
Jon Loeliger72eb0ef2007-07-04 22:32:19 -0500481#if defined(CONFIG_CMD_KGDB)
wdenkfe8c2802002-11-03 00:38:21 +0000482# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
483#endif
484
485/*-----------------------------------------------------------------------
486 * HIDx - Hardware Implementation-dependent Registers 2-11
487 *-----------------------------------------------------------------------
488 * HID0 also contains cache control - initially enable both caches and
489 * invalidate contents, then the final state leaves only the instruction
490 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
491 * but Soft reset does not.
492 *
493 * HID1 has only read-only information - nothing to set.
494 */
495#define CFG_HID0_INIT (HID0_ICE |\
wdenk8bde7f72003-06-27 21:31:46 +0000496 HID0_DCE |\
497 HID0_ICFI |\
498 HID0_DCI |\
499 HID0_IFEM |\
500 HID0_ABE)
wdenkfe8c2802002-11-03 00:38:21 +0000501
502#define CFG_HID0_FINAL (HID0_ICE |\
wdenk8bde7f72003-06-27 21:31:46 +0000503 HID0_IFEM |\
504 HID0_ABE |\
505 HID0_EMCP)
wdenkfe8c2802002-11-03 00:38:21 +0000506#define CFG_HID2 0
507
508/*-----------------------------------------------------------------------
509 * RMR - Reset Mode Register
510 *-----------------------------------------------------------------------
511 */
512#define CFG_RMR 0
513
514/*-----------------------------------------------------------------------
515 * BCR - Bus Configuration 4-25
516 *-----------------------------------------------------------------------
517 */
518#define CFG_BCR (BCR_ETM)
519
520/*-----------------------------------------------------------------------
521 * SIUMCR - SIU Module Configuration 4-31
522 *-----------------------------------------------------------------------
523 */
524#define CFG_SIUMCR (SIUMCR_DPPC11 |\
wdenk8bde7f72003-06-27 21:31:46 +0000525 SIUMCR_L2CPC00 |\
526 SIUMCR_APPC10 |\
527 SIUMCR_MMR00)
wdenkfe8c2802002-11-03 00:38:21 +0000528
529
530/*-----------------------------------------------------------------------
531 * SYPCR - System Protection Control 11-9
532 * SYPCR can only be written once after reset!
533 *-----------------------------------------------------------------------
534 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
535 */
536#define CFG_SYPCR (SYPCR_SWTC |\
wdenk8bde7f72003-06-27 21:31:46 +0000537 SYPCR_BMT |\
538 SYPCR_PBME |\
539 SYPCR_LBME |\
540 SYPCR_SWRI |\
541 SYPCR_SWP)
wdenkfe8c2802002-11-03 00:38:21 +0000542
543/*-----------------------------------------------------------------------
544 * TMCNTSC - Time Counter Status and Control 4-40
545 *-----------------------------------------------------------------------
546 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
547 * and enable Time Counter
548 */
549#define CFG_TMCNTSC (TMCNTSC_SEC |\
wdenk8bde7f72003-06-27 21:31:46 +0000550 TMCNTSC_ALR |\
551 TMCNTSC_TCF |\
552 TMCNTSC_TCE)
wdenkfe8c2802002-11-03 00:38:21 +0000553
554/*-----------------------------------------------------------------------
555 * PISCR - Periodic Interrupt Status and Control 4-42
556 *-----------------------------------------------------------------------
557 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
558 * Periodic timer
559 */
560#define CFG_PISCR (PISCR_PS |\
wdenk8bde7f72003-06-27 21:31:46 +0000561 PISCR_PTF |\
562 PISCR_PTE)
wdenkfe8c2802002-11-03 00:38:21 +0000563
564/*-----------------------------------------------------------------------
565 * SCCR - System Clock Control 9-8
566 *-----------------------------------------------------------------------
567 */
568#define CFG_SCCR 0
569
570/*-----------------------------------------------------------------------
571 * RCCR - RISC Controller Configuration 13-7
572 *-----------------------------------------------------------------------
573 */
574#define CFG_RCCR 0
575
576/*
577 * Initialize Memory Controller:
578 *
579 * Bank Bus Machine PortSz Device
580 * ---- --- ------- ------ ------
581 * 0 60x GPCM 32 bit FLASH (SIMM - 4MB)
582 * 1 60x GPCM 32 bit unused
583 * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
584 * 3 60x SDRAM 64 bit unused
585 * 4 Local GPCM 8 bit IO (on board - 64k)
586 * 5 60x GPCM 8 bit unused
587 * 6 60x GPCM 8 bit unused
588 * 7 60x GPCM 8 bit unused
589 *
590 */
591
592/*-----------------------------------------------------------------------
593 * BR0 - Base Register
594 * Ref: Section 10.3.1 on page 10-14
595 * OR0 - Option Register
596 * Ref: Section 10.3.2 on page 10-18
597 *-----------------------------------------------------------------------
598 */
599
600/* Bank 0,1 - FLASH SIMM
601 *
602 * This expects the FLASH SIMM to be connected to *CS0
603 * It consists of 4 AM29F016D parts.
604 *
605 * Note: For the 8 MB SIMM, *CS1 is unused.
606 */
607
608/* BR0 is configured as follows:
609 *
610 * - Base address of 0x40000000
611 * - 32 bit port size
612 * - Data errors checking is disabled
613 * - Read and write access
614 * - GPCM 60x bus
615 * - Access are handled by the memory controller according to MSEL
616 * - Not used for atomic operations
617 * - No data pipelining is done
618 * - Valid
619 */
620#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000621 BRx_PS_32 |\
622 BRx_MS_GPCM_P |\
623 BRx_V)
wdenkfe8c2802002-11-03 00:38:21 +0000624
625/* OR0 is configured as follows:
626 *
627 * - 8 MB
628 * - *BCTL0 is asserted upon access to the current memory bank
629 * - *CW / *WE are negated a quarter of a clock earlier
630 * - *CS is output at the same time as the address lines
631 * - Uses a clock cycle length of 5
632 * - *PSDVAL is generated internally by the memory controller
633 * unless *GTA is asserted earlier externally.
634 * - Relaxed timing is generated by the GPCM for accesses
635 * initiated to this memory region.
636 * - One idle clock is inserted between a read access from the
637 * current bank and the next access.
638 */
639#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000640 ORxG_CSNT |\
641 ORxG_ACS_DIV1 |\
642 ORxG_SCY_5_CLK |\
643 ORxG_TRLX |\
644 ORxG_EHTR)
wdenkfe8c2802002-11-03 00:38:21 +0000645
646/*-----------------------------------------------------------------------
647 * BR2 - Base Register
648 * Ref: Section 10.3.1 on page 10-14
649 * OR2 - Option Register
650 * Ref: Section 10.3.2 on page 10-16
651 *-----------------------------------------------------------------------
652 */
653
654/* Bank 2 - SDRAM DIMM
655 *
656 * 16MB DIMM: P/N
657 * 64MB DIMM: P/N 1W-8864X8-4-P1-EST or
658 * MT4LSDT864AG-10EB1 (Micron)
659 *
660 * Note: *CS3 is unused for this DIMM
661 */
662
663/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
664 *
665 * - Base address of 0x00000000
666 * - 64 bit port size (60x bus only)
667 * - Data errors checking is disabled
668 * - Read and write access
669 * - SDRAM 60x bus
670 * - Access are handled by the memory controller according to MSEL
671 * - Not used for atomic operations
672 * - No data pipelining is done
673 * - Valid
674 */
675#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000676 BRx_PS_64 |\
677 BRx_MS_SDRAM_P |\
678 BRx_V)
wdenkfe8c2802002-11-03 00:38:21 +0000679
680/* With a 16 MB DIMM, the OR2 is configured as follows:
681 *
682 * - 16 MB
683 * - 2 internal banks per device
684 * - Row start address bit is A9 with PSDMR[PBI] = 0
685 * - 11 row address lines
686 * - Back-to-back page mode
687 * - Internal bank interleaving within save device enabled
688 */
689#if (CFG_SDRAM0_SIZE == 16)
690#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000691 ORxS_BPD_2 |\
692 ORxS_ROWST_PBI0_A9 |\
693 ORxS_NUMR_11)
wdenkfe8c2802002-11-03 00:38:21 +0000694
695/* With a 16 MB DIMM, the PSDMR is configured as follows:
696 *
697 * - Page Based Interleaving,
698 * - Refresh Enable,
699 * - Address Multiplexing where A5 is output on A14 pin
700 * (A6 on A15, and so on),
701 * - use address pins A16-A18 as bank select,
702 * - A9 is output on SDA10 during an ACTIVATE command,
703 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
704 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
705 * is 3 clocks,
706 * - earliest timing for READ/WRITE command after ACTIVATE command is
707 * 2 clocks,
708 * - earliest timing for PRECHARGE after last data was read is 1 clock,
709 * - earliest timing for PRECHARGE after last data was written is 1 clock,
710 * - CAS Latency is 2.
711 */
712
713/*-----------------------------------------------------------------------
714 * PSDMR - 60x Bus SDRAM Mode Register
715 * Ref: Section 10.3.3 on page 10-21
716 *-----------------------------------------------------------------------
717 */
718#define CFG_PSDMR (PSDMR_RFEN |\
wdenk8bde7f72003-06-27 21:31:46 +0000719 PSDMR_SDAM_A14_IS_A5 |\
720 PSDMR_BSMA_A16_A18 |\
721 PSDMR_SDA10_PBI0_A9 |\
722 PSDMR_RFRC_7_CLK |\
723 PSDMR_PRETOACT_3W |\
724 PSDMR_ACTTORW_2W |\
725 PSDMR_LDOTOPRE_1C |\
726 PSDMR_WRC_1C |\
727 PSDMR_CL_2)
wdenkfe8c2802002-11-03 00:38:21 +0000728#endif /* (CFG_SDRAM0_SIZE == 16) */
729
730/* With a 64 MB DIMM, the OR2 is configured as follows:
731 *
732 * - 64 MB
733 * - 4 internal banks per device
734 * - Row start address bit is A8 with PSDMR[PBI] = 0
735 * - 12 row address lines
736 * - Back-to-back page mode
737 * - Internal bank interleaving within save device enabled
738 */
739#if (CFG_SDRAM0_SIZE == 64)
740#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000741 ORxS_BPD_4 |\
742 ORxS_ROWST_PBI0_A8 |\
743 ORxS_NUMR_12)
wdenkfe8c2802002-11-03 00:38:21 +0000744
745/* With a 64 MB DIMM, the PSDMR is configured as follows:
746 *
747 * - Page Based Interleaving,
748 * - Refresh Enable,
749 * - Address Multiplexing where A5 is output on A14 pin
750 * (A6 on A15, and so on),
751 * - use address pins A14-A16 as bank select,
752 * - A9 is output on SDA10 during an ACTIVATE command,
753 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
754 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
755 * is 3 clocks,
756 * - earliest timing for READ/WRITE command after ACTIVATE command is
757 * 2 clocks,
758 * - earliest timing for PRECHARGE after last data was read is 1 clock,
759 * - earliest timing for PRECHARGE after last data was written is 1 clock,
760 * - CAS Latency is 2.
761 */
762
763/*-----------------------------------------------------------------------
764 * PSDMR - 60x Bus SDRAM Mode Register
765 * Ref: Section 10.3.3 on page 10-21
766 *-----------------------------------------------------------------------
767 */
768#define CFG_PSDMR (PSDMR_RFEN |\
wdenk8bde7f72003-06-27 21:31:46 +0000769 PSDMR_SDAM_A14_IS_A5 |\
770 PSDMR_BSMA_A14_A16 |\
771 PSDMR_SDA10_PBI0_A9 |\
772 PSDMR_RFRC_7_CLK |\
773 PSDMR_PRETOACT_3W |\
774 PSDMR_ACTTORW_2W |\
775 PSDMR_LDOTOPRE_1C |\
776 PSDMR_WRC_1C |\
777 PSDMR_CL_2)
wdenkfe8c2802002-11-03 00:38:21 +0000778#endif /* (CFG_SDRAM0_SIZE == 64) */
779
780#define CFG_PSRT 0x0e
781#define CFG_MPTPR MPTPR_PTP_DIV32
782
783
784/*-----------------------------------------------------------------------
785 * BR4 - Base Register
786 * Ref: Section 10.3.1 on page 10-14
787 * OR4 - Option Register
788 * Ref: Section 10.3.2 on page 10-18
789 *-----------------------------------------------------------------------
790 */
791/* Bank 4 - Onboard Memory Mapped IO controller
792 *
793 * This expects the onboard IO controller to connected to *CS4 and
794 * the local bus.
795 * - Base address of 0xe0000000
796 * - 8 bit port size (local bus only)
797 * - Read and write access
798 * - GPCM local bus
799 * - Not used for atomic operations
800 * - No data pipelining is done
801 * - Valid
802 * - extended hold time
803 * - 11 wait states
804 */
805
806#ifdef CFG_IO_BASE
807# define CFG_BR4_PRELIM ((CFG_IO_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000808 BRx_PS_8 |\
809 BRx_MS_GPCM_L |\
810 BRx_V)
wdenkfe8c2802002-11-03 00:38:21 +0000811
812# define CFG_OR4_PRELIM (ORxG_AM_MSK |\
wdenk8bde7f72003-06-27 21:31:46 +0000813 ORxG_SCY_11_CLK |\
814 ORxG_EHTR)
wdenkfe8c2802002-11-03 00:38:21 +0000815#endif /* CFG_IO_BASE */
816
817/*
818 * Internal Definitions
819 *
820 * Boot Flags
821 */
822#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
823#define BOOTFLAG_WARM 0x02 /* Software reboot */
824
825#endif /* __CONFIG_H */