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Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
3 * (C) Copyright 2007 DENX Software Engineering
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * Derived from the MPC83xx header.
14 */
15
16#ifndef __MPC512X_H__
17#define __MPC512X_H__
18
19#include <config.h>
20#if defined(CONFIG_E300)
21#include <asm/e300.h>
22#endif
23
24/* System reset offset (PowerPC standard)
25 */
26#define EXC_OFF_SYS_RESET 0x0100
27#define _START_OFFSET EXC_OFF_SYS_RESET
28
29
30/* IMMRBAR - Internal Memory Register Base Address
31 */
32#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
33#define IMMRBAR 0x0000 /* Register offset to immr */
34#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
35#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
36
37/* LAWBAR - Local Access Window Base Address Register
38 */
39#define LPBAW 0x0020 /* Register offset to immr */
40#define LPCS0AW 0x0024
41#define LPCS1AW 0x0028
42#define LPCS2AW 0x002C
43#define LPCS3AW 0x0030
44#define LPCS4AW 0x0034
45#define LPCS5AW 0x0038
46#define LPCS6AW 0x003C
47#define LPCA7AW 0x0040
48#define SRAMBAR 0x00C4
49
50#define LPC_OFFSET 0x10000
51
52#define CS0_CONFIG 0x00000
53#define CS1_CONFIG 0x00004
54#define CS2_CONFIG 0x00008
55#define CS3_CONFIG 0x0000C
56#define CS4_CONFIG 0x00010
57#define CS5_CONFIG 0x00014
58#define CS6_CONFIG 0x00018
59#define CS7_CONFIG 0x0001C
60
61#define CS_CTRL 0x00020
62#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */
Wolfgang Denkb1b54e32007-08-02 21:27:46 +020063#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */
Rafal Jaworowski8993e542007-07-27 14:43:59 +020064
65/* SPRIDR - System Part and Revision ID Register
66 */
67#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
68#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
69
70#define SPR_5121E 0x80180000
71
72/* SPCR - System Priority Configuration Register
73 */
74#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
75#define SPCR_PCIHPE_SHIFT (31-3)
76#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */
77#define SPCR_PCIPR_SHIFT (31-7)
78#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */
79#define SPCR_TBEN_SHIFT (31-9)
80#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */
81#define SPCR_COREPR_SHIFT (31-11)
82
83/* SWCRR - System Watchdog Control Register
84 */
85#define SWCRR 0x0904 /* Register offset to immr */
86#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
87#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
88#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
89#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
90#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
91
92/* SWCNR - System Watchdog Counter Register
93 */
94#define SWCNR 0x0908 /* Register offset to immr */
95#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */
96#define SWCNR_RES ~(SWCNR_SWCN)
97
98/* SWSRR - System Watchdog Service Register
99 */
100#define SWSRR 0x090E /* Register offset to immr */
101
102/* ACR - Arbiter Configuration Register
103 */
104#define ACR_COREDIS 0x10000000 /* Core disable */
105#define ACR_COREDIS_SHIFT (31-7)
106#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
107#define ACR_PIPE_DEP_SHIFT (31-15)
108#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
109#define ACR_PCI_RPTCNT_SHIFT (31-19)
110#define ACR_RPTCNT 0x00000700 /* Repeat count */
111#define ACR_RPTCNT_SHIFT (31-23)
112#define ACR_APARK 0x00000030 /* Address parking */
113#define ACR_APARK_SHIFT (31-27)
114#define ACR_PARKM 0x0000000F /* Parking master */
115#define ACR_PARKM_SHIFT (31-31)
116
117/* ATR - Arbiter Timers Register
118 */
119#define ATR_DTO 0x00FF0000 /* Data time out */
120#define ATR_ATO 0x000000FF /* Address time out */
121
122/* AER - Arbiter Event Register
123 */
124#define AER_ETEA 0x00000020 /* Transfer error */
125#define AER_RES 0x00000010 /* Reserved transfer type */
126#define AER_ECW 0x00000008 /* External control word transfer type */
127#define AER_AO 0x00000004 /* Address Only transfer type */
128#define AER_DTO 0x00000002 /* Data time out */
129#define AER_ATO 0x00000001 /* Address time out */
130
131/* AEATR - Arbiter Event Address Register
132 */
133#define AEATR_EVENT 0x07000000 /* Event type */
134#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
135#define AEATR_TBST 0x00000800 /* Transfer burst */
136#define AEATR_TSIZE 0x00000700 /* Transfer Size */
137#define AEATR_TTYPE 0x0000001F /* Transfer Type */
138
139/* RSR - Reset Status Register
140 */
141#define RSR_SWSR 0x00002000 /* software soft reset */
142#define RSR_SWSR_SHIFT 13
143#define RSR_SWHR 0x00001000 /* software hard reset */
144#define RSR_SWHR_SHIFT 12
145#define RSR_JHRS 0x00000200 /* jtag hreset */
146#define RSR_JHRS_SHIFT 9
147#define RSR_JSRS 0x00000100 /* jtag sreset status */
148#define RSR_JSRS_SHIFT 8
149#define RSR_CSHR 0x00000010 /* checkstop reset status */
150#define RSR_CSHR_SHIFT 4
151#define RSR_SWRS 0x00000008 /* software watchdog reset status */
152#define RSR_SWRS_SHIFT 3
153#define RSR_BMRS 0x00000004 /* bus monitop reset status */
154#define RSR_BMRS_SHIFT 2
155#define RSR_SRS 0x00000002 /* soft reset status */
156#define RSR_SRS_SHIFT 1
157#define RSR_HRS 0x00000001 /* hard reset status */
158#define RSR_HRS_SHIFT 0
159#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\
160 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
161 RSR_BMRS | RSR_SRS | RSR_HRS)
162/* RMR - Reset Mode Register
163 */
164#define RMR_CSRE 0x00000001 /* checkstop reset enable */
165#define RMR_CSRE_SHIFT 0
166#define RMR_RES ~(RMR_CSRE)
167
168/* RCR - Reset Control Register
169 */
170#define RCR_SWHR 0x00000002 /* software hard reset */
171#define RCR_SWSR 0x00000001 /* software soft reset */
172#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
173
174/* RCER - Reset Control Enable Register
175 */
176#define RCER_CRE 0x00000001 /* software hard reset */
177#define RCER_RES ~(RCER_CRE)
178
179/* SPMR - System PLL Mode Register
180 */
181#define SPMR_SPMF 0x0F000000
182#define SPMR_SPMF_SHIFT 24
183#define SPMR_CPMF 0x000F0000
184#define SPMR_CPMF_SHIFT 16
185
186/* SCFR1 System Clock Frequency Register 1
187 */
John Rigbyde55d182008-01-30 13:36:56 -0700188#define SCFR1_IPS_DIV 0x3
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200189#define SCFR1_IPS_DIV_MASK 0x03800000
190#define SCFR1_IPS_DIV_SHIFT 23
191
192/* SCFR2 System Clock Frequency Register 2
193 */
194#define SCFR2_SYS_DIV 0xFC000000
195#define SCFR2_SYS_DIV_SHIFT 26
196
197/* SCCR - System Clock Control Registers
198 */
199
200/* System Clock Control Register 1 commands */
201#define CLOCK_SCCR1_CFG_EN 0x80000000
202#define CLOCK_SCCR1_LPC_EN 0x40000000
203#define CLOCK_SCCR1_NFC_EN 0x20000000
204#define CLOCK_SCCR1_PATA_EN 0x10000000
205#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn))
206#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000
207#define CLOCK_SCCR1_SATA_EN 0x00004000
208#define CLOCK_SCCR1_FEC_EN 0x00002000
209#define CLOCK_SCCR1_TPR_EN 0x00001000
210#define CLOCK_SCCR1_PCI_EN 0x00000800
211#define CLOCK_SCCR1_DDR_EN 0x00000400
212
213/* System Clock Control Register 2 commands */
214#define CLOCK_SCCR2_DIU_EN 0x80000000
215#define CLOCK_SCCR2_AXE_EN 0x40000000
216#define CLOCK_SCCR2_MEM_EN 0x20000000
217#define CLOCK_SCCR2_USB2_EN 0x10000000
218#define CLOCK_SCCR2_USB1_EN 0x08000000
219#define CLOCK_SCCR2_I2C_EN 0x04000000
220#define CLOCK_SCCR2_BDLC_EN 0x02000000
221#define CLOCK_SCCR2_SDHC_EN 0x01000000
222#define CLOCK_SCCR2_SPDIF_EN 0x00800000
223#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000
224#define CLOCK_SCCR2_MBX_EN 0x00200000
225#define CLOCK_SCCR2_MBX_3D_EN 0x00100000
226#define CLOCK_SCCR2_IIM_EN 0x00080000
227
228/* PSC FIFO Command values */
229#define PSC_FIFO_RESET_SLICE 0x80
230#define PSC_FIFO_ENABLE_SLICE 0x01
231
232/* PSC FIFO Controller Command values */
233#define FIFOC_ENABLE_CLOCK_GATE 0x01
234#define FIFOC_DISABLE_CLOCK_GATE 0x00
235
236/* PSC FIFO status */
237#define PSC_FIFO_EMPTY 0x01
238
239/* PSC Command values */
240#define PSC_RX_ENABLE 0x01
241#define PSC_RX_DISABLE 0x02
242#define PSC_TX_ENABLE 0x04
243#define PSC_TX_DISABLE 0x08
244#define PSC_SEL_MODE_REG_1 0x10
245#define PSC_RST_RX 0x20
246#define PSC_RST_TX 0x30
247#define PSC_RST_ERR_STAT 0x40
248#define PSC_RST_BRK_CHG_INT 0x50
249#define PSC_START_BRK 0x60
250#define PSC_STOP_BRK 0x70
251
252/* PSC status register bits */
253#define PSC_SR_CDE 0x0080
254#define PSC_SR_TXEMP 0x0800
255#define PSC_SR_OE 0x1000
256#define PSC_SR_PE 0x2000
257#define PSC_SR_FE 0x4000
258#define PSC_SR_RB 0x8000
259
260/* PSC mode fields */
261#define PSC_MODE_5_BITS 0x00
262#define PSC_MODE_6_BITS 0x01
263#define PSC_MODE_7_BITS 0x02
264#define PSC_MODE_8_BITS 0x03
265#define PSC_MODE_PAREVEN 0x00
266#define PSC_MODE_PARODD 0x04
267#define PSC_MODE_PARFORCE 0x08
268#define PSC_MODE_PARNONE 0x10
269#define PSC_MODE_ENTIMEOUT 0x20
270#define PSC_MODE_RXRTS 0x80
271#define PSC_MODE_1_STOPBIT 0x07
272
273/*
274 * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
275 *
276 * NOTE: individual PSC units are free to use whatever area (and size) of the
277 * FIFOC internal memory, so make sure memory areas for FIFO slices used by
278 * different PSCs do not overlap!
279 *
280 * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
281 * tests indicate that it is 1024 words total.
282 */
283#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */
284#define FIFOC_PSC0_TX_ADDR 0x0
285#define FIFOC_PSC0_RX_SIZE 0x0
286#define FIFOC_PSC0_RX_ADDR 0x0
287
288#define FIFOC_PSC1_TX_SIZE 0x0
289#define FIFOC_PSC1_TX_ADDR 0x0
290#define FIFOC_PSC1_RX_SIZE 0x0
291#define FIFOC_PSC1_RX_ADDR 0x0
292
293#define FIFOC_PSC2_TX_SIZE 0x0
294#define FIFOC_PSC2_TX_ADDR 0x0
295#define FIFOC_PSC2_RX_SIZE 0x0
296#define FIFOC_PSC2_RX_ADDR 0x0
297
298#define FIFOC_PSC3_TX_SIZE 0x04
299#define FIFOC_PSC3_TX_ADDR 0x0
300#define FIFOC_PSC3_RX_SIZE 0x04
301#define FIFOC_PSC3_RX_ADDR 0x10
302
303#define FIFOC_PSC4_TX_SIZE 0x0
304#define FIFOC_PSC4_TX_ADDR 0x0
305#define FIFOC_PSC4_RX_SIZE 0x0
306#define FIFOC_PSC4_RX_ADDR 0x0
307
308#define FIFOC_PSC5_TX_SIZE 0x0
309#define FIFOC_PSC5_TX_ADDR 0x0
310#define FIFOC_PSC5_RX_SIZE 0x0
311#define FIFOC_PSC5_RX_ADDR 0x0
312
313#define FIFOC_PSC6_TX_SIZE 0x0
314#define FIFOC_PSC6_TX_ADDR 0x0
315#define FIFOC_PSC6_RX_SIZE 0x0
316#define FIFOC_PSC6_RX_ADDR 0x0
317
318#define FIFOC_PSC7_TX_SIZE 0x0
319#define FIFOC_PSC7_TX_ADDR 0x0
320#define FIFOC_PSC7_RX_SIZE 0x0
321#define FIFOC_PSC7_RX_ADDR 0x0
322
323#define FIFOC_PSC8_TX_SIZE 0x0
324#define FIFOC_PSC8_TX_ADDR 0x0
325#define FIFOC_PSC8_RX_SIZE 0x0
326#define FIFOC_PSC8_RX_ADDR 0x0
327
328#define FIFOC_PSC9_TX_SIZE 0x0
329#define FIFOC_PSC9_TX_ADDR 0x0
330#define FIFOC_PSC9_RX_SIZE 0x0
331#define FIFOC_PSC9_RX_ADDR 0x0
332
333#define FIFOC_PSC10_TX_SIZE 0x0
334#define FIFOC_PSC10_TX_ADDR 0x0
335#define FIFOC_PSC10_RX_SIZE 0x0
336#define FIFOC_PSC10_RX_ADDR 0x0
337
338#define FIFOC_PSC11_TX_SIZE 0x0
339#define FIFOC_PSC11_TX_ADDR 0x0
340#define FIFOC_PSC11_RX_SIZE 0x0
341#define FIFOC_PSC11_RX_ADDR 0x0
342
343/* IO Control Register
344 */
345
346/* Indexes in regs array */
347#define MEM_IDX 0x00
John Rigby51b67d02007-08-24 18:18:43 -0600348#define PATA_CE1_IDX 0x2e
349#define PATA_CE2_IDX 0x2f
350#define PATA_ISOLATE_IDX 0x30
351#define PATA_IOR_IDX 0x31
352#define PATA_IOW_IDX 0x32
353#define PATA_IOCHRDY_IDX 0x33
354#define PATA_INTRQ_IDX 0x34
355#define PATA_DRQ_IDX 0x35
356#define PATA_DACK_IDX 0x36
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200357#define SPDIF_TXCLOCK_IDX 0x73
358#define SPDIF_TX_IDX 0x74
359#define SPDIF_RX_IDX 0x75
360#define PSC0_0_IDX 0x83
361#define PSC0_1_IDX 0x84
362#define PSC0_2_IDX 0x85
363#define PSC0_3_IDX 0x86
364#define PSC0_4_IDX 0x87
365#define PSC1_0_IDX 0x88
366#define PSC1_1_IDX 0x89
367#define PSC1_2_IDX 0x8a
368#define PSC1_3_IDX 0x8b
369#define PSC1_4_IDX 0x8c
370#define PSC2_0_IDX 0x8d
371#define PSC2_1_IDX 0x8e
372#define PSC2_2_IDX 0x8f
373#define PSC2_3_IDX 0x90
374#define PSC2_4_IDX 0x91
375
376#define IOCTRL_FUNCMUX_SHIFT 7
377#define IOCTRL_FUNCMUX_FEC 1
378#define IOCTRL_MUX_FEC (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT)
379
380/* Set for DDR */
381#define IOCTRL_MUX_DDR 0x00000036
382
383 /* Register Offset Base */
384#define MPC512X_FEC (CFG_IMMR + 0x02800)
385
386/* Number of I2C buses */
387#define I2C_BUS_CNT 3
388
389/* I2Cn control register bits */
390#define I2C_EN 0x80
391#define I2C_IEN 0x40
392#define I2C_STA 0x20
393#define I2C_TX 0x10
394#define I2C_TXAK 0x08
395#define I2C_RSTA 0x04
396#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
397
398/* I2Cn status register bits */
399#define I2C_CF 0x80
400#define I2C_AAS 0x40
401#define I2C_BB 0x20
402#define I2C_AL 0x10
403#define I2C_SRW 0x04
404#define I2C_IF 0x02
405#define I2C_RXAK 0x01
406
407#endif /* __MPC512X_H__ */