blob: 27e1a823c6175eb6fe45feef1e0c3736da23a6e6 [file] [log] [blame]
wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
Stefan Roese9b94ac62007-10-31 17:55:58 +010025#include <asm/cache.h>
wdenk0db5bca2003-03-31 17:27:09 +000026
wdenkaffae2b2002-08-17 09:36:01 +000027void flush_cache (ulong start_addr, ulong size)
28{
wdenk0db5bca2003-03-31 17:27:09 +000029#ifndef CONFIG_5xx
wdenkaffae2b2002-08-17 09:36:01 +000030 ulong addr, end_addr = start_addr + size;
31
32 if (CFG_CACHELINE_SIZE) {
33 addr = start_addr & (CFG_CACHELINE_SIZE - 1);
34 for (addr = start_addr;
35 addr < end_addr;
36 addr += CFG_CACHELINE_SIZE) {
37 asm ("dcbst 0,%0": :"r" (addr));
38 }
39 asm ("sync"); /* Wait for all dcbst to complete on bus */
40
41 for (addr = start_addr;
42 addr < end_addr;
43 addr += CFG_CACHELINE_SIZE) {
44 asm ("icbi 0,%0": :"r" (addr));
45 }
46 }
47 asm ("sync"); /* Always flush prefetch queue in any case */
48 asm ("isync");
wdenk0db5bca2003-03-31 17:27:09 +000049#endif
wdenkaffae2b2002-08-17 09:36:01 +000050}