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Wolfgang Denkad5bb452007-03-06 18:08:43 +01001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkad5bb452007-03-06 18:08:43 +01006 */
7
8#include <common.h>
9
10/* Memory test
11 *
12 * General observations:
13 * o The recommended test sequence is to test the data lines: if they are
14 * broken, nothing else will work properly. Then test the address
15 * lines. Finally, test the cells in the memory now that the test
16 * program knows that the address and data lines work properly.
17 * This sequence also helps isolate and identify what is faulty.
18 *
19 * o For the address line test, it is a good idea to use the base
20 * address of the lowest memory location, which causes a '1' bit to
21 * walk through a field of zeros on the address lines and the highest
22 * memory location, which causes a '0' bit to walk through a field of
23 * '1's on the address line.
24 *
25 * o Floating buses can fool memory tests if the test routine writes
26 * a value and then reads it back immediately. The problem is, the
27 * write will charge the residual capacitance on the data bus so the
28 * bus retains its state briefely. When the test program reads the
29 * value back immediately, the capacitance of the bus can allow it
30 * to read back what was written, even though the memory circuitry
31 * is broken. To avoid this, the test program should write a test
32 * pattern to the target location, write a different pattern elsewhere
33 * to charge the residual capacitance in a differnt manner, then read
34 * the target location back.
35 *
36 * o Always read the target location EXACTLY ONCE and save it in a local
37 * variable. The problem with reading the target location more than
38 * once is that the second and subsequent reads may work properly,
39 * resulting in a failed test that tells the poor technician that
40 * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
41 * doesn't help him one bit and causes puzzled phone calls. Been there,
42 * done that.
43 *
44 * Data line test:
45 * ---------------
46 * This tests data lines for shorts and opens by forcing adjacent data
47 * to opposite states. Because the data lines could be routed in an
48 * arbitrary manner the must ensure test patterns ensure that every case
49 * is tested. By using the following series of binary patterns every
50 * combination of adjacent bits is test regardless of routing.
51 *
52 * ...101010101010101010101010
53 * ...110011001100110011001100
54 * ...111100001111000011110000
55 * ...111111110000000011111111
56 *
57 * Carrying this out, gives us six hex patterns as follows:
58 *
59 * 0xaaaaaaaaaaaaaaaa
60 * 0xcccccccccccccccc
61 * 0xf0f0f0f0f0f0f0f0
62 * 0xff00ff00ff00ff00
63 * 0xffff0000ffff0000
64 * 0xffffffff00000000
65 *
66 * To test for short and opens to other signals on our boards, we
67 * simply test with the 1's complemnt of the paterns as well, resulting
68 * in twelve patterns total.
69 *
70 * After writing a test pattern. a special pattern 0x0123456789ABCDEF is
71 * written to a different address in case the data lines are floating.
72 * Thus, if a byte lane fails, you will see part of the special
73 * pattern in that byte lane when the test runs. For example, if the
74 * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
75 * (for the 'a' test pattern).
76 *
77 * Address line test:
78 * ------------------
79 * This function performs a test to verify that all the address lines
80 * hooked up to the RAM work properly. If there is an address line
81 * fault, it usually shows up as two different locations in the address
82 * map (related by the faulty address line) mapping to one physical
83 * memory storage location. The artifact that shows up is writing to
84 * the first location "changes" the second location.
85 *
86 * To test all address lines, we start with the given base address and
87 * xor the address with a '1' bit to flip one address line. For each
88 * test, we shift the '1' bit left to test the next address line.
89 *
90 * In the actual code, we start with address sizeof(ulong) since our
91 * test pattern we use is a ulong and thus, if we tried to test lower
92 * order address bits, it wouldn't work because our pattern would
93 * overwrite itself.
94 *
95 * Example for a 4 bit address space with the base at 0000:
96 * 0000 <- base
97 * 0001 <- test 1
98 * 0010 <- test 2
99 * 0100 <- test 3
100 * 1000 <- test 4
101 * Example for a 4 bit address space with the base at 0010:
102 * 0010 <- base
103 * 0011 <- test 1
104 * 0000 <- (below the base address, skipped)
105 * 0110 <- test 2
106 * 1010 <- test 3
107 *
108 * The test locations are successively tested to make sure that they are
109 * not "mirrored" onto the base address due to a faulty address line.
110 * Note that the base and each test location are related by one address
111 * line flipped. Note that the base address need not be all zeros.
112 *
113 * Memory tests 1-4:
114 * -----------------
115 * These tests verify RAM using sequential writes and reads
116 * to/from RAM. There are several test cases that use different patterns to
117 * verify RAM. Each test case fills a region of RAM with one pattern and
118 * then reads the region back and compares its contents with the pattern.
119 * The following patterns are used:
120 *
121 * 1a) zero pattern (0x00000000)
122 * 1b) negative pattern (0xffffffff)
123 * 1c) checkerboard pattern (0x55555555)
124 * 1d) checkerboard pattern (0xaaaaaaaa)
125 * 2) bit-flip pattern ((1 << (offset % 32))
126 * 3) address pattern (offset)
127 * 4) address pattern (~offset)
128 *
129 * Being run in normal mode, the test verifies only small 4Kb
130 * regions of RAM around each 1Mb boundary. For example, for 64Mb
131 * RAM the following areas are verified: 0x00000000-0x00000800,
132 * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
133 * 0x04000000. If the test is run in slow-test mode, it verifies
134 * the whole RAM.
135 */
136
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100137#include <post.h>
138#include <watchdog.h>
139
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000140#if CONFIG_POST & (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_MEM_REGIONS)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100141
142DECLARE_GLOBAL_DATA_PTR;
143
144/*
145 * Define INJECT_*_ERRORS for testing error detection in the presence of
146 * _good_ hardware.
147 */
148#undef INJECT_DATA_ERRORS
149#undef INJECT_ADDRESS_ERRORS
150
151#ifdef INJECT_DATA_ERRORS
152#warning "Injecting data line errors for testing purposes"
153#endif
154
155#ifdef INJECT_ADDRESS_ERRORS
156#warning "Injecting address line errors for testing purposes"
157#endif
158
159
160/*
161 * This function performs a double word move from the data at
162 * the source pointer to the location at the destination pointer.
163 * This is helpful for testing memory on processors which have a 64 bit
164 * wide data bus.
165 *
166 * On those PowerPC with FPU, use assembly and a floating point move:
167 * this does a 64 bit move.
168 *
169 * For other processors, let the compiler generate the best code it can.
170 */
Anatolij Gustschin44b4dbe2008-02-25 23:53:07 +0100171static void move64(const unsigned long long *src, unsigned long long *dest)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100172{
Masahiro Yamadad622ac32014-12-15 23:26:31 +0900173#if defined(CONFIG_MPC8260)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100174 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
175 "stfd 0, 0(4)" /* *dest = fpr0 */
176 : : : "fr0" ); /* Clobbers fr0 */
177 return;
178#else
179 *dest = *src;
180#endif
181}
182
183/*
184 * This is 64 bit wide test patterns. Note that they reside in ROM
185 * (which presumably works) and the tests write them to RAM which may
186 * not work.
187 *
188 * The "otherpattern" is written to drive the data bus to values other
189 * than the test pattern. This is for detecting floating bus lines.
190 *
191 */
192const static unsigned long long pattern[] = {
193 0xaaaaaaaaaaaaaaaaULL,
194 0xccccccccccccccccULL,
195 0xf0f0f0f0f0f0f0f0ULL,
196 0xff00ff00ff00ff00ULL,
197 0xffff0000ffff0000ULL,
198 0xffffffff00000000ULL,
199 0x00000000ffffffffULL,
200 0x0000ffff0000ffffULL,
201 0x00ff00ff00ff00ffULL,
202 0x0f0f0f0f0f0f0f0fULL,
203 0x3333333333333333ULL,
204 0x5555555555555555ULL
205};
206const unsigned long long otherpattern = 0x0123456789abcdefULL;
207
208
209static int memory_post_dataline(unsigned long long * pmem)
210{
211 unsigned long long temp64 = 0;
Mike Frysingerd2397812011-05-10 07:28:35 +0000212 int num_patterns = ARRAY_SIZE(pattern);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100213 int i;
214 unsigned int hi, lo, pathi, patlo;
215 int ret = 0;
216
217 for ( i = 0; i < num_patterns; i++) {
Anatolij Gustschin44b4dbe2008-02-25 23:53:07 +0100218 move64(&(pattern[i]), pmem++);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100219 /*
220 * Put a different pattern on the data lines: otherwise they
221 * may float long enough to read back what we wrote.
222 */
Anatolij Gustschin44b4dbe2008-02-25 23:53:07 +0100223 move64(&otherpattern, pmem--);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100224 move64(pmem, &temp64);
225
226#ifdef INJECT_DATA_ERRORS
227 temp64 ^= 0x00008000;
228#endif
229
230 if (temp64 != pattern[i]){
231 pathi = (pattern[i]>>32) & 0xffffffff;
232 patlo = pattern[i] & 0xffffffff;
233
234 hi = (temp64>>32) & 0xffffffff;
235 lo = temp64 & 0xffffffff;
236
Valentin Longchampca51d052011-08-03 02:37:03 +0000237 post_log("Memory (date line) error at %08x, "
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100238 "wrote %08x%08x, read %08x%08x !\n",
239 pmem, pathi, patlo, hi, lo);
240 ret = -1;
241 }
242 }
243 return ret;
244}
245
246static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
247{
248 ulong *target;
249 ulong *end;
250 ulong readback;
251 ulong xor;
252 int ret = 0;
253
254 end = (ulong *)((ulong)base + size); /* pointer arith! */
255 xor = 0;
256 for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
257 target = (ulong *)((ulong)testaddr ^ xor);
258 if((target >= base) && (target < end)) {
259 *testaddr = ~*target;
260 readback = *target;
261
262#ifdef INJECT_ADDRESS_ERRORS
263 if(xor == 0x00008000) {
264 readback = *testaddr;
265 }
266#endif
267 if(readback == *testaddr) {
Valentin Longchampca51d052011-08-03 02:37:03 +0000268 post_log("Memory (address line) error at %08x<->%08x, "
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200269 "XOR value %08x !\n",
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100270 testaddr, target, xor);
271 ret = -1;
272 }
273 }
274 }
275 return ret;
276}
277
Valentin Longchampca51d052011-08-03 02:37:03 +0000278static int memory_post_test1(unsigned long start,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100279 unsigned long size,
280 unsigned long val)
281{
282 unsigned long i;
283 ulong *mem = (ulong *) start;
284 ulong readback;
285 int ret = 0;
286
287 for (i = 0; i < size / sizeof (ulong); i++) {
288 mem[i] = val;
289 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000290 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100291 }
292
Valentin Longchampca51d052011-08-03 02:37:03 +0000293 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100294 readback = mem[i];
295 if (readback != val) {
Valentin Longchampca51d052011-08-03 02:37:03 +0000296 post_log("Memory error at %08x, "
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100297 "wrote %08x, read %08x !\n",
298 mem + i, val, readback);
299
300 ret = -1;
301 break;
302 }
303 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000304 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100305 }
306
307 return ret;
308}
309
Valentin Longchampca51d052011-08-03 02:37:03 +0000310static int memory_post_test2(unsigned long start, unsigned long size)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100311{
312 unsigned long i;
313 ulong *mem = (ulong *) start;
314 ulong readback;
315 int ret = 0;
316
317 for (i = 0; i < size / sizeof (ulong); i++) {
318 mem[i] = 1 << (i % 32);
319 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000320 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100321 }
322
Valentin Longchampca51d052011-08-03 02:37:03 +0000323 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100324 readback = mem[i];
325 if (readback != (1 << (i % 32))) {
Valentin Longchampca51d052011-08-03 02:37:03 +0000326 post_log("Memory error at %08x, "
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100327 "wrote %08x, read %08x !\n",
328 mem + i, 1 << (i % 32), readback);
329
330 ret = -1;
331 break;
332 }
333 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000334 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100335 }
336
337 return ret;
338}
339
Valentin Longchampca51d052011-08-03 02:37:03 +0000340static int memory_post_test3(unsigned long start, unsigned long size)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100341{
342 unsigned long i;
343 ulong *mem = (ulong *) start;
344 ulong readback;
345 int ret = 0;
346
347 for (i = 0; i < size / sizeof (ulong); i++) {
348 mem[i] = i;
349 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000350 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100351 }
352
Valentin Longchampca51d052011-08-03 02:37:03 +0000353 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100354 readback = mem[i];
355 if (readback != i) {
Valentin Longchampca51d052011-08-03 02:37:03 +0000356 post_log("Memory error at %08x, "
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100357 "wrote %08x, read %08x !\n",
358 mem + i, i, readback);
359
360 ret = -1;
361 break;
362 }
363 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000364 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100365 }
366
367 return ret;
368}
369
Valentin Longchampca51d052011-08-03 02:37:03 +0000370static int memory_post_test4(unsigned long start, unsigned long size)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100371{
372 unsigned long i;
373 ulong *mem = (ulong *) start;
374 ulong readback;
375 int ret = 0;
376
377 for (i = 0; i < size / sizeof (ulong); i++) {
378 mem[i] = ~i;
379 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000380 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100381 }
382
Valentin Longchampca51d052011-08-03 02:37:03 +0000383 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100384 readback = mem[i];
385 if (readback != ~i) {
Valentin Longchampca51d052011-08-03 02:37:03 +0000386 post_log("Memory error at %08x, "
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100387 "wrote %08x, read %08x !\n",
388 mem + i, ~i, readback);
389
390 ret = -1;
391 break;
392 }
393 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000394 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100395 }
396
397 return ret;
398}
399
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000400static int memory_post_test_lines(unsigned long start, unsigned long size)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100401{
402 int ret = 0;
403
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000404 ret = memory_post_dataline((unsigned long long *)start);
Valentin Longchampca51d052011-08-03 02:37:03 +0000405 WATCHDOG_RESET();
406 if (!ret)
407 ret = memory_post_addrline((ulong *)start, (ulong *)start,
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000408 size);
Valentin Longchampca51d052011-08-03 02:37:03 +0000409 WATCHDOG_RESET();
410 if (!ret)
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000411 ret = memory_post_addrline((ulong *)(start+size-8),
412 (ulong *)start, size);
Valentin Longchampca51d052011-08-03 02:37:03 +0000413 WATCHDOG_RESET();
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000414
415 return ret;
416}
417
418static int memory_post_test_patterns(unsigned long start, unsigned long size)
419{
420 int ret = 0;
421
422 ret = memory_post_test1(start, size, 0x00000000);
Valentin Longchampca51d052011-08-03 02:37:03 +0000423 WATCHDOG_RESET();
424 if (!ret)
425 ret = memory_post_test1(start, size, 0xffffffff);
426 WATCHDOG_RESET();
427 if (!ret)
428 ret = memory_post_test1(start, size, 0x55555555);
429 WATCHDOG_RESET();
430 if (!ret)
431 ret = memory_post_test1(start, size, 0xaaaaaaaa);
432 WATCHDOG_RESET();
433 if (!ret)
434 ret = memory_post_test2(start, size);
435 WATCHDOG_RESET();
436 if (!ret)
437 ret = memory_post_test3(start, size);
438 WATCHDOG_RESET();
439 if (!ret)
440 ret = memory_post_test4(start, size);
441 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100442
443 return ret;
444}
445
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000446static int memory_post_test_regions(unsigned long start, unsigned long size)
447{
448 unsigned long i;
449 int ret = 0;
450
451 for (i = 0; i < (size >> 20) && (!ret); i++) {
452 if (!ret)
Heiko Schocher7b5d61b2011-10-06 20:40:00 +0000453 ret = memory_post_test_patterns(start + (i << 20),
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000454 0x800);
Heiko Schocher7b5d61b2011-10-06 20:40:00 +0000455 if (!ret)
456 ret = memory_post_test_patterns(start + (i << 20) +
457 0xff800, 0x800);
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000458 }
459
460 return ret;
461}
462
463static int memory_post_tests(unsigned long start, unsigned long size)
464{
465 int ret = 0;
466
467 ret = memory_post_test_lines(start, size);
468 if (!ret)
469 ret = memory_post_test_patterns(start, size);
470
471 return ret;
472}
473
Heiko Schocher42042982011-06-02 19:38:24 +0000474/*
475 * !! this is only valid, if you have contiguous memory banks !!
476 */
York Sun28417032010-09-28 15:20:31 -0700477__attribute__((weak))
478int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100479{
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100480 bd_t *bd = gd->bd;
Heiko Schocher42042982011-06-02 19:38:24 +0000481
York Sun28417032010-09-28 15:20:31 -0700482 *vstart = CONFIG_SYS_SDRAM_BASE;
Heiko Schocher42042982011-06-02 19:38:24 +0000483 *size = (gd->ram_size >= 256 << 20 ?
484 256 << 20 : gd->ram_size) - (1 << 20);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100485
Yuri Tikhonov9c02def2007-08-25 05:07:16 +0200486 /* Limit area to be tested with the board info struct */
York Sun28417032010-09-28 15:20:31 -0700487 if ((*vstart) + (*size) > (ulong)bd)
488 *size = (ulong)bd - *vstart;
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100489
York Sun28417032010-09-28 15:20:31 -0700490 return 0;
491}
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100492
York Sun28417032010-09-28 15:20:31 -0700493__attribute__((weak))
494int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
495{
496 return 1;
497}
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100498
York Sun28417032010-09-28 15:20:31 -0700499__attribute__((weak))
500int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
501{
502 return 0;
503}
504
505__attribute__((weak))
506void arch_memory_failure_handle(void)
507{
508 return;
509}
510
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000511int memory_regions_post_test(int flags)
512{
513 int ret = 0;
514 phys_addr_t phys_offset = 0;
515 u32 memsize, vstart;
516
517 arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
518
519 ret = memory_post_test_lines(vstart, memsize);
520 if (!ret)
521 ret = memory_post_test_regions(vstart, memsize);
522
523 return ret;
524}
525
York Sun28417032010-09-28 15:20:31 -0700526int memory_post_test(int flags)
527{
528 int ret = 0;
529 phys_addr_t phys_offset = 0;
530 u32 memsize, vstart;
531
532 arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
533
534 do {
535 if (flags & POST_SLOWTEST) {
536 ret = memory_post_tests(vstart, memsize);
537 } else { /* POST_NORMAL */
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000538 ret = memory_post_test_regions(vstart, memsize);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100539 }
York Sun28417032010-09-28 15:20:31 -0700540 } while (!ret &&
541 !arch_memory_test_advance(&vstart, &memsize, &phys_offset));
542
543 arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
544 if (ret)
545 arch_memory_failure_handle();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100546
547 return ret;
548}
549
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000550#endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) */