blob: 3f809c0dbb956cb64e6c20e84db4251b3b98c680 [file] [log] [blame]
weichangzhengb9d0f002022-03-02 15:09:05 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Phytium Pomelo board
4 * Copyright (C) 2021, Phytium Ltd.
5 * lixinde <lixinde@phytium.com.cn>
6 * weichangzheng <weichangzheng@phytium.com.cn>
7 */
8/dts-v1/;
9
10/ {
11 model = "Phytium Pomelo Board";
12 compatible = "phytium,d2000-pomelo", "phytium,d2000";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 aliases {
17 serial0 = &uart0;
18 };
19
20 sysclk_48mhz: clk48mhz {
21 compatible = "fixed-clock";
22 #clock-cells = <0x0>;
23 clock-frequency = <48000000>;
24 clock-output-names = "sysclk_48mhz";
25 };
26
27 soc {
28 compatible = "simple-bus";
29 #address-cells = <2>;
30 #size-cells = <2>;
31 ranges;
32
33 uart0: serial@28001000 {
34 compatible = "arm,pl011", "arm,primecell";
35 reg = <0x0 0x28001000 0x0 0x1000>;
36 clocks = <&sysclk_48mhz>;
37 };
38
39 pcie@40000000 {
40 compatible = "pci-host-ecam-generic";
41 device_type = "pci";
42 #address-cells = <3>;
43 #size-cells = <2>;
44 reg = <0x0 0x40000000 0x0 0x10000000>;
45 ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>,
46 <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>,
47 <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;
48 };
49 };
50};