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Tom Warrene23bb6a2013-01-28 13:32:10 +00001/*
Jimmy Zhangb9dd6212014-01-24 10:37:36 -07002 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
Tom Warrene23bb6a2013-01-28 13:32:10 +00003 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra114 Clock control functions */
18
19#include <common.h>
20#include <asm/io.h>
21#include <asm/arch/clock.h>
Tom Warrenb40f7342013-04-01 15:48:54 -070022#include <asm/arch/sysctr.h>
Tom Warrene23bb6a2013-01-28 13:32:10 +000023#include <asm/arch/tegra.h>
24#include <asm/arch-tegra/clk_rst.h>
25#include <asm/arch-tegra/timer.h>
26#include <div64.h>
27#include <fdtdec.h>
28
29/*
30 * Clock types that we can use as a source. The Tegra114 has muxes for the
31 * peripheral clocks, and in most cases there are four options for the clock
32 * source. This gives us a clock 'type' and exploits what commonality exists
33 * in the device.
34 *
35 * Letters are obvious, except for T which means CLK_M, and S which means the
36 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
37 * datasheet) and PLL_M are different things. The former is the basic
38 * clock supplied to the SOC from an external oscillator. The latter is the
39 * memory clock PLL.
40 *
41 * See definitions in clock_id in the header file.
42 */
43enum clock_type_id {
44 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
45 CLOCK_TYPE_MCPA, /* and so on */
46 CLOCK_TYPE_MCPT,
47 CLOCK_TYPE_PCM,
48 CLOCK_TYPE_PCMT,
49 CLOCK_TYPE_PCMT16,
50 CLOCK_TYPE_PDCT,
51 CLOCK_TYPE_ACPT,
52 CLOCK_TYPE_ASPTE,
53 CLOCK_TYPE_PMDACD2T,
54 CLOCK_TYPE_PCST,
55
56 CLOCK_TYPE_COUNT,
57 CLOCK_TYPE_NONE = -1, /* invalid clock type */
58};
59
60enum {
61 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
62};
63
Tom Warrene23bb6a2013-01-28 13:32:10 +000064/*
65 * Clock source mux for each clock type. This just converts our enum into
66 * a list of mux sources for use by the code.
67 *
68 * Note:
69 * The extra column in each clock source array is used to store the mask
70 * bits in its register for the source.
71 */
72#define CLK(x) CLOCK_ID_ ## x
73static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
74 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
75 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
76 MASK_BITS_31_30},
77 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
78 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
79 MASK_BITS_31_30},
80 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
81 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
82 MASK_BITS_31_30},
83 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
84 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
85 MASK_BITS_31_30},
86 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
87 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
88 MASK_BITS_31_30},
89 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
90 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
91 MASK_BITS_31_30},
92 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
93 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
94 MASK_BITS_31_30},
95 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
96 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
97 MASK_BITS_31_30},
98 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
99 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
100 MASK_BITS_31_29},
101 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
102 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
103 MASK_BITS_31_29},
104 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
105 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Stephen Warren5916a362014-01-24 10:16:18 -0700106 MASK_BITS_31_28}
Tom Warrene23bb6a2013-01-28 13:32:10 +0000107};
108
109/*
110 * Clock type for each peripheral clock source. We put the name in each
111 * record just so it is easy to match things up
112 */
113#define TYPE(name, type) type
114static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
115 /* 0x00 */
116 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
117 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
118 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
119 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
120 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
121 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
122 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
123 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
124
125 /* 0x08 */
126 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
127 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
128 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16),
129 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
130 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
131 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
132 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
133 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
134
135 /* 0x10 */
136 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
137 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
138 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
139 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
140 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
141 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
142 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
143 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
144
145 /* 0x18 */
146 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
147 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
148 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
149 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
150 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
151 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
152 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
153 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
154
155 /* 0x20 */
156 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
157 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
158 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
159 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
160 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
161 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
162 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
163 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
164
165 /* 0x28 */
166 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
167 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
168 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
169 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
170 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
171 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
172 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
173 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
174
175 /* 0x30 */
176 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
177 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
178 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
179 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
180 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
181 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
182 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
183 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
184
185 /* 0x38h */ /* Jumps to reg offset 0x3B0h */
186 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
187 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
188 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
189 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
190 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
191 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
192 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
193 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
194
195 /* 0x40 */
196 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
197 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
198 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
199 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
200 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
201 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
202 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
203 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
204
205 /* 0x48 */
206 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
207 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
208 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
209 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
210 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
211 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
212 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
213 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
214
215 /* 0x50 */
216 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
217 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
218 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
219 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
220 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
221 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
222 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
223};
224
225/*
226 * This array translates a periph_id to a periphc_internal_id
227 *
228 * Not present/matched up:
229 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
230 * SPDIF - which is both 0x08 and 0x0c
231 *
232 */
233#define NONE(name) (-1)
234#define OFFSET(name, value) PERIPHC_ ## name
235static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
236 /* Low word: 31:0 */
237 NONE(CPU),
238 NONE(COP),
239 NONE(TRIGSYS),
240 NONE(RESERVED3),
241 NONE(RTC),
242 NONE(TMR),
243 PERIPHC_UART1,
244 PERIPHC_UART2, /* and vfir 0x68 */
245
246 /* 8 */
247 NONE(GPIO),
248 PERIPHC_SDMMC2,
249 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
250 PERIPHC_I2S1,
251 PERIPHC_I2C1,
252 PERIPHC_NDFLASH,
253 PERIPHC_SDMMC1,
254 PERIPHC_SDMMC4,
255
256 /* 16 */
257 NONE(RESERVED16),
258 PERIPHC_PWM,
259 PERIPHC_I2S2,
260 PERIPHC_EPP,
261 PERIPHC_VI,
262 PERIPHC_G2D,
263 NONE(USBD),
264 NONE(ISP),
265
266 /* 24 */
267 PERIPHC_G3D,
268 NONE(RESERVED25),
269 PERIPHC_DISP2,
270 PERIPHC_DISP1,
271 PERIPHC_HOST1X,
272 NONE(VCP),
273 PERIPHC_I2S0,
274 NONE(CACHE2),
275
276 /* Middle word: 63:32 */
277 NONE(MEM),
278 NONE(AHBDMA),
279 NONE(APBDMA),
280 NONE(RESERVED35),
281 NONE(RESERVED36),
282 NONE(STAT_MON),
283 NONE(RESERVED38),
284 NONE(RESERVED39),
285
286 /* 40 */
287 NONE(KFUSE),
288 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
289 PERIPHC_NOR,
290 NONE(RESERVED43),
291 PERIPHC_SBC2,
292 NONE(RESERVED45),
293 PERIPHC_SBC3,
294 PERIPHC_I2C5,
295
296 /* 48 */
297 NONE(DSI),
298 PERIPHC_TVO, /* also CVE 0x40 */
299 PERIPHC_MIPI,
300 PERIPHC_HDMI,
301 NONE(CSI),
302 PERIPHC_TVDAC,
303 PERIPHC_I2C2,
304 PERIPHC_UART3,
305
306 /* 56 */
307 NONE(RESERVED56),
308 PERIPHC_EMC,
309 NONE(USB2),
310 NONE(USB3),
311 PERIPHC_MPE,
312 PERIPHC_VDE,
313 NONE(BSEA),
314 NONE(BSEV),
315
316 /* Upper word 95:64 */
317 PERIPHC_SPEEDO,
318 PERIPHC_UART4,
319 PERIPHC_UART5,
320 PERIPHC_I2C3,
321 PERIPHC_SBC4,
322 PERIPHC_SDMMC3,
323 NONE(PCIE),
324 PERIPHC_OWR,
325
326 /* 72 */
327 NONE(AFI),
328 PERIPHC_CSITE,
329 NONE(PCIEXCLK),
330 NONE(AVPUCQ),
331 NONE(RESERVED76),
332 NONE(RESERVED77),
333 NONE(RESERVED78),
334 NONE(DTV),
335
336 /* 80 */
337 PERIPHC_NANDSPEED,
338 PERIPHC_I2CSLOW,
339 NONE(DSIB),
340 NONE(RESERVED83),
341 NONE(IRAMA),
342 NONE(IRAMB),
343 NONE(IRAMC),
344 NONE(IRAMD),
345
346 /* 88 */
347 NONE(CRAM2),
348 NONE(RESERVED89),
349 NONE(MDOUBLER),
350 NONE(RESERVED91),
351 NONE(SUSOUT),
352 NONE(RESERVED93),
353 NONE(RESERVED94),
354 NONE(RESERVED95),
355
356 /* V word: 31:0 */
357 NONE(CPUG),
358 NONE(CPULP),
359 PERIPHC_G3D2,
360 PERIPHC_MSELECT,
361 PERIPHC_TSENSOR,
362 PERIPHC_I2S3,
363 PERIPHC_I2S4,
364 PERIPHC_I2C4,
365
366 /* 08 */
367 PERIPHC_SBC5,
368 PERIPHC_SBC6,
369 PERIPHC_AUDIO,
370 NONE(APBIF),
371 PERIPHC_DAM0,
372 PERIPHC_DAM1,
373 PERIPHC_DAM2,
374 PERIPHC_HDA2CODEC2X,
375
376 /* 16 */
377 NONE(ATOMICS),
378 NONE(RESERVED17),
379 NONE(RESERVED18),
380 NONE(RESERVED19),
381 NONE(RESERVED20),
382 NONE(RESERVED21),
383 NONE(RESERVED22),
384 PERIPHC_ACTMON,
385
386 /* 24 */
387 NONE(RESERVED24),
388 NONE(RESERVED25),
389 NONE(RESERVED26),
390 NONE(RESERVED27),
391 PERIPHC_SATA,
392 PERIPHC_HDA,
393 NONE(RESERVED30),
394 NONE(RESERVED31),
395
396 /* W word: 31:0 */
397 NONE(HDA2HDMICODEC),
398 NONE(RESERVED1_SATACOLD),
399 NONE(RESERVED2_PCIERX0),
400 NONE(RESERVED3_PCIERX1),
401 NONE(RESERVED4_PCIERX2),
402 NONE(RESERVED5_PCIERX3),
403 NONE(RESERVED6_PCIERX4),
404 NONE(RESERVED7_PCIERX5),
405
406 /* 40 */
407 NONE(CEC),
408 NONE(PCIE2_IOBIST),
409 NONE(EMC_IOBIST),
410 NONE(HDMI_IOBIST),
411 NONE(SATA_IOBIST),
412 NONE(MIPI_IOBIST),
413 NONE(EMC1_IOBIST),
414 NONE(XUSB),
415
416 /* 48 */
417 NONE(CILAB),
418 NONE(CILCD),
419 NONE(CILE),
420 NONE(DSIA_LP),
421 NONE(DSIB_LP),
422 NONE(RESERVED21_ENTROPY),
423 NONE(RESERVED22_W),
424 NONE(RESERVED23_W),
425
426 /* 56 */
427 NONE(RESERVED24_W),
428 NONE(AMX0),
429 NONE(ADX0),
430 NONE(DVFS),
431 NONE(XUSB_SS),
432 NONE(EMC_DLL),
433 NONE(MC1),
434 NONE(EMC1),
435};
436
437/*
438 * Get the oscillator frequency, from the corresponding hardware configuration
439 * field. Note that T30/T114 support 3 new higher freqs, but we map back
440 * to the old T20 freqs. Support for the higher oscillators is TBD.
441 */
442enum clock_osc_freq clock_get_osc_freq(void)
443{
444 struct clk_rst_ctlr *clkrst =
445 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
446 u32 reg;
447
448 reg = readl(&clkrst->crc_osc_ctrl);
449 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
450
451 if (reg & 1) /* one of the newer freqs */
452 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
453
454 return reg >> 2; /* Map to most common (T20) freqs */
455}
456
457/* Returns a pointer to the clock source register for a peripheral */
458u32 *get_periph_source_reg(enum periph_id periph_id)
459{
460 struct clk_rst_ctlr *clkrst =
461 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
462 enum periphc_internal_id internal_id;
463
464 /* Coresight is a special case */
465 if (periph_id == PERIPH_ID_CSI)
466 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
467
468 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
469 internal_id = periph_id_to_internal_id[periph_id];
470 assert(internal_id != -1);
471 if (internal_id >= PERIPHC_VW_FIRST) {
472 internal_id -= PERIPHC_VW_FIRST;
473 return &clkrst->crc_clk_src_vw[internal_id];
474 } else
475 return &clkrst->crc_clk_src[internal_id];
476}
477
478/**
479 * Given a peripheral ID and the required source clock, this returns which
480 * value should be programmed into the source mux for that peripheral.
481 *
482 * There is special code here to handle the one source type with 5 sources.
483 *
484 * @param periph_id peripheral to start
485 * @param source PLL id of required parent clock
486 * @param mux_bits Set to number of bits in mux register: 2 or 4
487 * @param divider_bits Set to number of divider bits (8 or 16)
488 * @return mux value (0-4, or -1 if not found)
489 */
490int get_periph_clock_source(enum periph_id periph_id,
491 enum clock_id parent, int *mux_bits, int *divider_bits)
492{
493 enum clock_type_id type;
494 enum periphc_internal_id internal_id;
495 int mux;
496
497 assert(clock_periph_id_isvalid(periph_id));
498
499 internal_id = periph_id_to_internal_id[periph_id];
500 assert(periphc_internal_id_isvalid(internal_id));
501
502 type = clock_periph_type[internal_id];
503 assert(clock_type_id_isvalid(type));
504
505 *mux_bits = clock_source[type][CLOCK_MAX_MUX];
506
507 if (type == CLOCK_TYPE_PCMT16)
508 *divider_bits = 16;
509 else
510 *divider_bits = 8;
511
512 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
513 if (clock_source[type][mux] == parent)
514 return mux;
515
516 /* if we get here, either us or the caller has made a mistake */
517 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
518 parent);
519 return -1;
520}
521
522void clock_set_enable(enum periph_id periph_id, int enable)
523{
524 struct clk_rst_ctlr *clkrst =
525 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
526 u32 *clk;
527 u32 reg;
528
529 /* Enable/disable the clock to this peripheral */
530 assert(clock_periph_id_isvalid(periph_id));
531 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
532 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
533 else
534 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
535 reg = readl(clk);
536 if (enable)
537 reg |= PERIPH_MASK(periph_id);
538 else
539 reg &= ~PERIPH_MASK(periph_id);
540 writel(reg, clk);
541}
542
543void reset_set_enable(enum periph_id periph_id, int enable)
544{
545 struct clk_rst_ctlr *clkrst =
546 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
547 u32 *reset;
548 u32 reg;
549
550 /* Enable/disable reset to the peripheral */
551 assert(clock_periph_id_isvalid(periph_id));
552 if (periph_id < PERIPH_ID_VW_FIRST)
553 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
554 else
555 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
556 reg = readl(reset);
557 if (enable)
558 reg |= PERIPH_MASK(periph_id);
559 else
560 reg &= ~PERIPH_MASK(periph_id);
561 writel(reg, reset);
562}
563
564#ifdef CONFIG_OF_CONTROL
565/*
566 * Convert a device tree clock ID to our peripheral ID. They are mostly
567 * the same but we are very cautious so we check that a valid clock ID is
568 * provided.
569 *
570 * @param clk_id Clock ID according to tegra114 device tree binding
571 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
572 */
573enum periph_id clk_id_to_periph_id(int clk_id)
574{
575 if (clk_id > PERIPH_ID_COUNT)
576 return PERIPH_ID_NONE;
577
578 switch (clk_id) {
579 case PERIPH_ID_RESERVED3:
580 case PERIPH_ID_RESERVED16:
581 case PERIPH_ID_RESERVED24:
582 case PERIPH_ID_RESERVED35:
583 case PERIPH_ID_RESERVED43:
584 case PERIPH_ID_RESERVED45:
585 case PERIPH_ID_RESERVED56:
586 case PERIPH_ID_RESERVED76:
587 case PERIPH_ID_RESERVED77:
588 case PERIPH_ID_RESERVED78:
589 case PERIPH_ID_RESERVED83:
590 case PERIPH_ID_RESERVED89:
591 case PERIPH_ID_RESERVED91:
592 case PERIPH_ID_RESERVED93:
593 case PERIPH_ID_RESERVED94:
594 case PERIPH_ID_RESERVED95:
595 return PERIPH_ID_NONE;
596 default:
597 return clk_id;
598 }
599}
600#endif /* CONFIG_OF_CONTROL */
601
602void clock_early_init(void)
603{
604 struct clk_rst_ctlr *clkrst =
605 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
606
Jimmy Zhangb9dd6212014-01-24 10:37:36 -0700607 tegra30_set_up_pllp();
608
Tom Warrene23bb6a2013-01-28 13:32:10 +0000609 /*
Tom Warrene23bb6a2013-01-28 13:32:10 +0000610 * PLLC output frequency set to 600Mhz
611 * PLLD output frequency set to 925Mhz
612 */
613 switch (clock_get_osc_freq()) {
614 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
Tom Warrene23bb6a2013-01-28 13:32:10 +0000615 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
616 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
617 break;
618
619 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
Tom Warrene23bb6a2013-01-28 13:32:10 +0000620 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
621 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
622 break;
623
624 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
Tom Warrene23bb6a2013-01-28 13:32:10 +0000625 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
626 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
627 break;
628 case CLOCK_OSC_FREQ_19_2:
629 default:
630 /*
631 * These are not supported. It is too early to print a
632 * message and the UART likely won't work anyway due to the
633 * oscillator being wrong.
634 */
635 break;
636 }
637
638 /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
639 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
640
641 /* PLLC_MISC: Set LOCK_ENABLE */
642 writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
643 udelay(2);
644
645 /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
646 writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
647 udelay(2);
648}
Tom Warrenb40f7342013-04-01 15:48:54 -0700649
650void arch_timer_init(void)
651{
652 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
653 u32 freq, val;
654
655 freq = clock_get_rate(CLOCK_ID_OSC);
656 debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
657
658 /* ARM CNTFRQ */
659 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
660
661 /* Only T114 has the System Counter regs */
662 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
663 writel(freq, &sysctr->cntfid0);
664
665 val = readl(&sysctr->cntcr);
666 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
667 writel(val, &sysctr->cntcr);
668 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
669}