blob: fcd55c7743ad62244599b7f5632fc9eaa65892a3 [file] [log] [blame]
wdenk03f5c552004-10-10 21:21:55 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk03f5c552004-10-10 21:21:55 +00003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenk03f5c552004-10-10 21:21:55 +00005 */
6
7/*
8 * mpc8555cds board configuration file
9 *
10 * Please refer to doc/README.mpc85xxcds for more info.
11 *
12 */
wdenk03f5c552004-10-10 21:21:55 +000013#ifndef __CONFIG_H
14#define __CONFIG_H
15
York Sun9ae14ca2015-08-18 12:35:52 -070016#define CONFIG_DISPLAY_BOARDINFO
17
wdenk03f5c552004-10-10 21:21:55 +000018/* High Level Configuration Options */
19#define CONFIG_BOOKE 1 /* BOOKE */
20#define CONFIG_E500 1 /* BOOKE e500 family */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050021#define CONFIG_CPM2 1 /* has CPM2 */
wdenk03f5c552004-10-10 21:21:55 +000022#define CONFIG_MPC8555 1 /* MPC8555 specific */
23#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
24
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0xfff80000
26
wdenk03f5c552004-10-10 21:21:55 +000027#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000028#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala0151cba2008-10-21 11:33:58 -050029#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020030#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk03f5c552004-10-10 21:21:55 +000031#define CONFIG_ENV_OVERWRITE
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060032#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk03f5c552004-10-10 21:21:55 +000033
Jon Loeliger25eedb22008-03-19 15:02:07 -050034#define CONFIG_FSL_VIA
Timur Tabie8d18542008-07-18 16:52:23 +020035
wdenk03f5c552004-10-10 21:21:55 +000036#ifndef __ASSEMBLY__
37extern unsigned long get_clock_freq(void);
38#endif
39#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
40
41/*
42 * These can be toggled for performance analysis, otherwise use default.
43 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020044#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk03f5c552004-10-10 21:21:55 +000045#define CONFIG_BTB /* toggle branch predition */
wdenk03f5c552004-10-10 21:21:55 +000046
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
48#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk03f5c552004-10-10 21:21:55 +000049
Timur Tabie46fedf2011-08-04 18:03:41 -050050#define CONFIG_SYS_CCSRBAR 0xe0000000
51#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk03f5c552004-10-10 21:21:55 +000052
Jon Loeliger2b40edb2008-03-18 11:12:42 -050053/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070054#define CONFIG_SYS_FSL_DDR1
Jon Loeliger2b40edb2008-03-18 11:12:42 -050055#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
56#define CONFIG_DDR_SPD
57#undef CONFIG_FSL_DDR_INTERACTIVE
58
59#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
60
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
62#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk03f5c552004-10-10 21:21:55 +000063
Jon Loeliger2b40edb2008-03-18 11:12:42 -050064#define CONFIG_NUM_DDR_CONTROLLERS 1
65#define CONFIG_DIMM_SLOTS_PER_CTLR 1
66#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk03f5c552004-10-10 21:21:55 +000067
Jon Loeliger2b40edb2008-03-18 11:12:42 -050068/* I2C addresses of SPD EEPROMs */
69#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
70
71/* Make sure required options are set */
wdenk03f5c552004-10-10 21:21:55 +000072#ifndef CONFIG_SPD_EEPROM
73#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
74#endif
75
Jon Loeliger7202d432005-07-25 11:13:26 -050076#undef CONFIG_CLOCKS_IN_MHZ
77
wdenk03f5c552004-10-10 21:21:55 +000078/*
Jon Loeliger7202d432005-07-25 11:13:26 -050079 * Local Bus Definitions
wdenk03f5c552004-10-10 21:21:55 +000080 */
Jon Loeliger7202d432005-07-25 11:13:26 -050081
82/*
83 * FLASH on the Local Bus
84 * Two banks, 8M each, using the CFI driver.
85 * Boot from BR0/OR0 bank at 0xff00_0000
86 * Alternate BR1/OR1 bank at 0xff80_0000
87 *
88 * BR0, BR1:
89 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
90 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
91 * Port Size = 16 bits = BRx[19:20] = 10
92 * Use GPCM = BRx[24:26] = 000
93 * Valid = BRx[31] = 1
94 *
95 * 0 4 8 12 16 20 24 28
96 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
97 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
98 *
99 * OR0, OR1:
100 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
101 * Reserved ORx[17:18] = 11, confusion here?
102 * CSNT = ORx[20] = 1
103 * ACS = half cycle delay = ORx[21:22] = 11
104 * SCY = 6 = ORx[24:27] = 0110
105 * TRLX = use relaxed timing = ORx[29] = 1
106 * EAD = use external address latch delay = OR[31] = 1
107 *
108 * 0 4 8 12 16 20 24 28
109 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
110 */
111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
wdenk03f5c552004-10-10 21:21:55 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_BR0_PRELIM 0xff801001
115#define CONFIG_SYS_BR1_PRELIM 0xff001001
wdenk03f5c552004-10-10 21:21:55 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_OR0_PRELIM 0xff806e65
118#define CONFIG_SYS_OR1_PRELIM 0xff806e65
wdenk03f5c552004-10-10 21:21:55 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
121#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
122#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
123#undef CONFIG_SYS_FLASH_CHECKSUM
124#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
125#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk03f5c552004-10-10 21:21:55 +0000126
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk03f5c552004-10-10 21:21:55 +0000128
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200129#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_CFI
131#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk03f5c552004-10-10 21:21:55 +0000132
wdenk03f5c552004-10-10 21:21:55 +0000133/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500134 * SDRAM on the Local Bus
wdenk03f5c552004-10-10 21:21:55 +0000135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
137#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk03f5c552004-10-10 21:21:55 +0000138
139/*
140 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk03f5c552004-10-10 21:21:55 +0000142 *
143 * For BR2, need:
144 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
145 * port-size = 32-bits = BR2[19:20] = 11
146 * no parity checking = BR2[21:22] = 00
147 * SDRAM for MSEL = BR2[24:26] = 011
148 * Valid = BR[31] = 1
149 *
150 * 0 4 8 12 16 20 24 28
151 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
152 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk03f5c552004-10-10 21:21:55 +0000154 * FIXME: the top 17 bits of BR2.
155 */
156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk03f5c552004-10-10 21:21:55 +0000158
159/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk03f5c552004-10-10 21:21:55 +0000161 *
162 * For OR2, need:
163 * 64MB mask for AM, OR2[0:7] = 1111 1100
164 * XAM, OR2[17:18] = 11
165 * 9 columns OR2[19-21] = 010
166 * 13 rows OR2[23-25] = 100
167 * EAD set for extra time OR[31] = 1
168 *
169 * 0 4 8 12 16 20 24 28
170 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
171 */
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk03f5c552004-10-10 21:21:55 +0000174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
176#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
177#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
178#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
wdenk03f5c552004-10-10 21:21:55 +0000179
180/*
wdenk03f5c552004-10-10 21:21:55 +0000181 * Common settings for all Local Bus SDRAM commands.
182 * At run time, either BSMA1516 (for CPU 1.1)
183 * or BSMA1617 (for CPU 1.0) (old)
184 * is OR'ed in too.
185 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500186#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
187 | LSDMR_PRETOACT7 \
188 | LSDMR_ACTTORW7 \
189 | LSDMR_BL8 \
190 | LSDMR_WRC4 \
191 | LSDMR_CL3 \
192 | LSDMR_RFEN \
wdenk03f5c552004-10-10 21:21:55 +0000193 )
194
195/*
196 * The CADMUS registers are connected to CS3 on CDS.
197 * The new memory map places CADMUS at 0xf8000000.
198 *
199 * For BR3, need:
200 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
201 * port-size = 8-bits = BR[19:20] = 01
202 * no parity checking = BR[21:22] = 00
203 * GPMC for MSEL = BR[24:26] = 000
204 * Valid = BR[31] = 1
205 *
206 * 0 4 8 12 16 20 24 28
207 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
208 *
209 * For OR3, need:
210 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
211 * disable buffer ctrl OR[19] = 0
212 * CSNT OR[20] = 1
213 * ACS OR[21:22] = 11
214 * XACS OR[23] = 1
215 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
216 * SETA OR[28] = 0
217 * TRLX OR[29] = 1
218 * EHTR OR[30] = 1
219 * EAD extra time OR[31] = 1
220 *
221 * 0 4 8 12 16 20 24 28
222 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
223 */
224
Jon Loeliger25eedb22008-03-19 15:02:07 -0500225#define CONFIG_FSL_CADMUS
226
wdenk03f5c552004-10-10 21:21:55 +0000227#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_BR3_PRELIM 0xf8000801
229#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
wdenk03f5c552004-10-10 21:21:55 +0000230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_INIT_RAM_LOCK 1
232#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200233#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk03f5c552004-10-10 21:21:55 +0000234
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200235#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk03f5c552004-10-10 21:21:55 +0000237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
239#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk03f5c552004-10-10 21:21:55 +0000240
241/* Serial Port */
242#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_NS16550_SERIAL
244#define CONFIG_SYS_NS16550_REG_SIZE 1
245#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk03f5c552004-10-10 21:21:55 +0000246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk03f5c552004-10-10 21:21:55 +0000248 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
251#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk03f5c552004-10-10 21:21:55 +0000252
Jon Loeliger20476722006-10-20 15:50:15 -0500253/*
254 * I2C
255 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200256#define CONFIG_SYS_I2C
257#define CONFIG_SYS_I2C_FSL
258#define CONFIG_SYS_FSL_I2C_SPEED 400000
259#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
260#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
261#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk03f5c552004-10-10 21:21:55 +0000262
Timur Tabie8d18542008-07-18 16:52:23 +0200263/* EEPROM */
264#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_I2C_EEPROM_CCID
266#define CONFIG_SYS_ID_EEPROM
267#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
268#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200269
wdenk03f5c552004-10-10 21:21:55 +0000270/*
271 * General PCI
272 * Addresses are mapped 1-1.
273 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600274#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600275#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600276#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600278#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600279#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
281#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000282
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600283#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600284#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600285#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600287#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600288#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
290#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000291
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700292#ifdef CONFIG_LEGACY
293#define BRIDGE_ID 17
294#define VIA_ID 2
295#else
296#define BRIDGE_ID 28
297#define VIA_ID 4
298#endif
wdenk03f5c552004-10-10 21:21:55 +0000299
300#if defined(CONFIG_PCI)
301
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200302#define CONFIG_PCI_PNP /* do pci plug-and-play */
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500303#define CONFIG_MPC85XX_PCI2
wdenk03f5c552004-10-10 21:21:55 +0000304
305#undef CONFIG_EEPRO100
306#undef CONFIG_TULIP
307
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500308#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk03f5c552004-10-10 21:21:55 +0000310
311#endif /* CONFIG_PCI */
312
wdenk03f5c552004-10-10 21:21:55 +0000313#if defined(CONFIG_TSEC_ENET)
314
wdenk03f5c552004-10-10 21:21:55 +0000315#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500316#define CONFIG_TSEC1 1
317#define CONFIG_TSEC1_NAME "TSEC0"
318#define CONFIG_TSEC2 1
319#define CONFIG_TSEC2_NAME "TSEC1"
wdenk03f5c552004-10-10 21:21:55 +0000320#define TSEC1_PHY_ADDR 0
321#define TSEC2_PHY_ADDR 1
wdenk03f5c552004-10-10 21:21:55 +0000322#define TSEC1_PHYIDX 0
323#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500324#define TSEC1_FLAGS TSEC_GIGABIT
325#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500326
327/* Options are: TSEC[0-1] */
328#define CONFIG_ETHPRIME "TSEC0"
wdenk03f5c552004-10-10 21:21:55 +0000329
330#endif /* CONFIG_TSEC_ENET */
331
wdenk03f5c552004-10-10 21:21:55 +0000332/*
333 * Environment
334 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200335#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200337#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
338#define CONFIG_ENV_SIZE 0x2000
wdenk03f5c552004-10-10 21:21:55 +0000339
340#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk03f5c552004-10-10 21:21:55 +0000342
Jon Loeliger2835e512007-06-13 13:22:08 -0500343/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500344 * BOOTP options
345 */
346#define CONFIG_BOOTP_BOOTFILESIZE
347#define CONFIG_BOOTP_BOOTPATH
348#define CONFIG_BOOTP_GATEWAY
349#define CONFIG_BOOTP_HOSTNAME
350
Jon Loeliger659e2f62007-07-10 09:10:49 -0500351/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500352 * Command line configuration.
353 */
Kumar Gala1c9aa762008-09-22 23:40:42 -0500354#define CONFIG_CMD_IRQ
Becky Bruce199e2622010-06-17 11:37:25 -0500355#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500356
wdenk03f5c552004-10-10 21:21:55 +0000357#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500358 #define CONFIG_CMD_PCI
wdenk03f5c552004-10-10 21:21:55 +0000359#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500360
wdenk03f5c552004-10-10 21:21:55 +0000361#undef CONFIG_WATCHDOG /* watchdog disabled */
362
363/*
364 * Miscellaneous configurable options
365 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500367#define CONFIG_CMDLINE_EDITING /* Command-line editing */
368#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeliger2835e512007-06-13 13:22:08 -0500370#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000372#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000374#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
376#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
377#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000378
379/*
380 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500381 * have to be in the first 64 MB of memory, since this is
wdenk03f5c552004-10-10 21:21:55 +0000382 * the maximum mapped by the Linux kernel during initialization.
383 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500384#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
385#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk03f5c552004-10-10 21:21:55 +0000386
Jon Loeliger2835e512007-06-13 13:22:08 -0500387#if defined(CONFIG_CMD_KGDB)
wdenk03f5c552004-10-10 21:21:55 +0000388#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk03f5c552004-10-10 21:21:55 +0000389#endif
390
wdenk03f5c552004-10-10 21:21:55 +0000391/*
392 * Environment Configuration
393 */
wdenk03f5c552004-10-10 21:21:55 +0000394#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500395#define CONFIG_HAS_ETH0
wdenke2ffd592004-12-31 09:32:47 +0000396#define CONFIG_HAS_ETH1
wdenke2ffd592004-12-31 09:32:47 +0000397#define CONFIG_HAS_ETH2
wdenk03f5c552004-10-10 21:21:55 +0000398#endif
399
400#define CONFIG_IPADDR 192.168.1.253
401
402#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000403#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000404#define CONFIG_BOOTFILE "your.uImage"
wdenk03f5c552004-10-10 21:21:55 +0000405
406#define CONFIG_SERVERIP 192.168.1.1
407#define CONFIG_GATEWAYIP 192.168.1.1
408#define CONFIG_NETMASK 255.255.255.0
409
410#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
411
wdenk03f5c552004-10-10 21:21:55 +0000412#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
413
414#define CONFIG_BAUDRATE 115200
415
416#define CONFIG_EXTRA_ENV_SETTINGS \
417 "netdev=eth0\0" \
418 "consoledev=ttyS1\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500419 "ramdiskaddr=600000\0" \
420 "ramdiskfile=your.ramdisk.u-boot\0" \
421 "fdtaddr=400000\0" \
422 "fdtfile=your.fdt.dtb\0"
wdenk03f5c552004-10-10 21:21:55 +0000423
424#define CONFIG_NFSBOOTCOMMAND \
425 "setenv bootargs root=/dev/nfs rw " \
426 "nfsroot=$serverip:$rootpath " \
427 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
428 "console=$consoledev,$baudrate $othbootargs;" \
429 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500430 "tftp $fdtaddr $fdtfile;" \
431 "bootm $loadaddr - $fdtaddr"
wdenk03f5c552004-10-10 21:21:55 +0000432
433#define CONFIG_RAMBOOTCOMMAND \
434 "setenv bootargs root=/dev/ram rw " \
435 "console=$consoledev,$baudrate $othbootargs;" \
436 "tftp $ramdiskaddr $ramdiskfile;" \
437 "tftp $loadaddr $bootfile;" \
438 "bootm $loadaddr $ramdiskaddr"
439
440#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
441
wdenk03f5c552004-10-10 21:21:55 +0000442#endif /* __CONFIG_H */