blob: 1f39ac4c173f06338c469c486e2919435e6f4b80 [file] [log] [blame]
Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
3 * (C) Copyright 2007 DENX Software Engineering
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * CPU specific code for the MPC512x family.
26 *
27 * Derived from the MPC83xx code.
28 */
29
30#include <common.h>
31#include <command.h>
32#include <mpc512x.h>
33#include <asm/processor.h>
34
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +010035#if defined(CONFIG_OF_LIBFDT)
36#include <fdt_support.h>
37#endif
38
Rafal Jaworowski8993e542007-07-27 14:43:59 +020039DECLARE_GLOBAL_DATA_PTR;
40
41int checkcpu (void)
42{
43 volatile immap_t *immr = (immap_t *) CFG_IMMR;
44 ulong clock = gd->cpu_clk;
45 u32 pvr = get_pvr ();
46 u32 spridr = immr->sysconf.spridr;
47 char buf[32];
48
Wolfgang Denk77d19a82007-08-12 21:34:34 +020049 puts ("CPU: ");
Rafal Jaworowski8993e542007-07-27 14:43:59 +020050
51 switch (spridr & 0xffff0000) {
52 case SPR_5121E:
53 puts ("MPC5121e ");
54 break;
55 default:
56 printf ("Unknown part ID %08x ", spridr & 0xffff0000);
57 }
58 printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
59
60 switch (pvr & 0xffff0000) {
61 case PVR_E300C4:
62 puts ("e300c4 ");
63 break;
64 default:
65 puts ("unknown ");
66 }
67 printf ("at %s MHz, CSB at %3d MHz\n", strmhz(buf, clock),
68 gd->csb_clk / 1000000);
69 return 0;
70}
71
72
73int
74do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
75{
76 ulong msr;
77 volatile immap_t *immap = (immap_t *) CFG_IMMR;
78
79 /* Interrupts and MMU off */
80 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
81
82 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
83 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
84
85 /*
86 * Enable Reset Control Reg - "RSTE" is the magic word that let us go
87 */
88 immap->reset.rpr = 0x52535445;
89
90 /* Verify Reset Control Reg is enabled */
91 while (!((immap->reset.rcer) & RCER_CRE))
92 ;
93
94 printf ("Resetting the board.\n");
95 udelay(200);
96
97 /* Perform reset */
98 immap->reset.rcr = RCR_SWHR;
99
100 /* Unreached... */
101 return 1;
102}
103
104
105/*
106 * Get timebase clock frequency (like cpu_clk in Hz)
107 */
108unsigned long get_tbclk (void)
109{
110 ulong tbclk;
111
112 tbclk = (gd->bus_clk + 3L) / 4L;
113
114 return tbclk;
115}
116
117
118#if defined(CONFIG_WATCHDOG)
119void watchdog_reset (void)
120{
121 int re_enable = disable_interrupts ();
122
123 /* Reset watchdog */
124 volatile immap_t *immr = (immap_t *) CFG_IMMR;
125 immr->wdt.swsrr = 0x556c;
126 immr->wdt.swsrr = 0xaa39;
127
128 if (re_enable)
129 enable_interrupts ();
130}
131#endif
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100132
133#ifdef CONFIG_OF_LIBFDT
John Rigbyef11df62008-08-05 17:38:57 -0600134
135#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
136/*
137 * fdt setup for old device trees
138 * fix up
139 * cpu clocks
140 * soc clocks
141 * ethernet addresses
142 */
143static void old_ft_cpu_setup(void *blob, bd_t *bd)
144{
145 /*
146 * avoid fixing up by path because that
147 * produces scary error messages
148 */
149
150 /*
151 * old device trees have ethernet nodes with
152 * device_type = "network"
153 */
154 do_fixup_by_prop(blob, "device_type", "network", 8,
155 "local-mac-address", bd->bi_enetaddr, 6, 0);
156 do_fixup_by_prop(blob, "device_type", "network", 8,
157 "address", bd->bi_enetaddr, 6, 0);
158 /*
159 * old device trees have soc nodes with
160 * device_type = "soc"
161 */
162 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
163 "bus-frequency", bd->bi_ipsfreq, 0);
164}
165#endif
166
167static void ft_clock_setup(void *blob, bd_t *bd)
168{
John Rigbyef11df62008-08-05 17:38:57 -0600169 char *cpu_path = "/cpus/" OF_CPU;
John Rigbyef11df62008-08-05 17:38:57 -0600170
171 /*
172 * fixup cpu clocks using path
173 */
174 do_fixup_by_path_u32(blob, cpu_path,
175 "timebase-frequency", OF_TBCLK, 1);
176 do_fixup_by_path_u32(blob, cpu_path,
177 "bus-frequency", bd->bi_busfreq, 1);
178 do_fixup_by_path_u32(blob, cpu_path,
179 "clock-frequency", bd->bi_intfreq, 1);
180 /*
181 * fixup soc clocks using compatible
182 */
183 do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
184 "bus-frequency", bd->bi_ipsfreq, 1);
185}
186
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100187void ft_cpu_setup(void *blob, bd_t *bd)
188{
John Rigbyef11df62008-08-05 17:38:57 -0600189#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
190 old_ft_cpu_setup(blob, bd);
191#endif
192 ft_clock_setup(blob, bd);
193#ifdef CONFIG_HAS_ETH0
Kumar Galaba37aa02008-08-19 15:41:18 -0500194 fdt_fixup_ethernet(blob);
John Rigbyef11df62008-08-05 17:38:57 -0600195#endif
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100196}
197#endif