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Ryder Lee090543f2018-11-15 10:07:57 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Watchdog driver for MediaTek SoCs
4 *
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 */
8
9#include <common.h>
10#include <dm.h>
Simon Glassdb41d652019-12-28 10:45:07 -070011#include <hang.h>
Ryder Lee090543f2018-11-15 10:07:57 +080012#include <wdt.h>
13#include <asm/io.h>
14
15#define MTK_WDT_MODE 0x00
16#define MTK_WDT_LENGTH 0x04
17#define MTK_WDT_RESTART 0x08
18#define MTK_WDT_STATUS 0x0c
19#define MTK_WDT_INTERVAL 0x10
20#define MTK_WDT_SWRST 0x14
21#define MTK_WDT_REQ_MODE 0x30
22#define MTK_WDT_DEBUG_CTL 0x40
23
24#define WDT_MODE_KEY (0x22 << 24)
25#define WDT_MODE_EN BIT(0)
26#define WDT_MODE_EXTPOL BIT(1)
27#define WDT_MODE_EXTEN BIT(2)
28#define WDT_MODE_IRQ_EN BIT(3)
29#define WDT_MODE_DUAL_EN BIT(6)
30
31#define WDT_LENGTH_KEY 0x8
32#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
33
34#define WDT_RESTART_KEY 0x1971
35#define WDT_SWRST_KEY 0x1209
36
37struct mtk_wdt_priv {
38 void __iomem *base;
39};
40
41static int mtk_wdt_reset(struct udevice *dev)
42{
43 struct mtk_wdt_priv *priv = dev_get_priv(dev);
44
45 /* Reload watchdog duration */
46 writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
47
48 return 0;
49}
50
51static int mtk_wdt_stop(struct udevice *dev)
52{
53 struct mtk_wdt_priv *priv = dev_get_priv(dev);
54
55 clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY);
56
57 return 0;
58}
59
60static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
61{
62 struct mtk_wdt_priv *priv = dev_get_priv(dev);
63
64 /* Kick watchdog to prevent counter == 0 */
65 writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
66
67 /* Reset */
68 writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST);
69 hang();
70
71 return 0;
72}
73
Stefan Roesec07f68d2019-07-03 07:22:20 +020074static void mtk_wdt_set_timeout(struct udevice *dev, u64 timeout_ms)
Ryder Lee090543f2018-11-15 10:07:57 +080075{
76 struct mtk_wdt_priv *priv = dev_get_priv(dev);
Stefan Roesec07f68d2019-07-03 07:22:20 +020077 u64 timeout_us;
78 u32 timeout_cc;
79 u32 length;
Ryder Lee090543f2018-11-15 10:07:57 +080080
81 /*
Shannon Barber2bc18212019-06-07 20:48:19 +000082 * One WDT_LENGTH count is 512 ticks of the wdt clock
83 * Clock runs at 32768 Hz
84 * e.g. 15.625 ms per count (nominal)
85 * We want the ceiling after dividing timeout_ms by 15.625 ms
86 * We add 15624 prior to the divide to implement the ceiling
87 * We prevent over-flow by clamping the timeout_ms value here
88 * as the maximum WDT_LENGTH counts is 1023 -> 15.984375 sec
89 * We also enforce a minimum of 1 count
90 * Many watchdog peripherals have a self-imposed count of 1
91 * that is added to the register counts.
92 * The MediaTek docs lack details to know if this is the case here.
93 * So we enforce a minimum of 1 to guarantee operation.
Ryder Lee090543f2018-11-15 10:07:57 +080094 */
Stefan Roesec07f68d2019-07-03 07:22:20 +020095 if (timeout_ms > 15984)
96 timeout_ms = 15984;
97
98 timeout_us = timeout_ms * 1000;
99 timeout_cc = (15624 + timeout_us) / 15625;
100 if (timeout_cc == 0)
101 timeout_cc = 1;
102
103 length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
Shannon Barber2bc18212019-06-07 20:48:19 +0000104 writel(length, priv->base + MTK_WDT_LENGTH);
Ryder Lee090543f2018-11-15 10:07:57 +0800105}
106
Stefan Roesec07f68d2019-07-03 07:22:20 +0200107static int mtk_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
Ryder Lee090543f2018-11-15 10:07:57 +0800108{
109 struct mtk_wdt_priv *priv = dev_get_priv(dev);
110
Stefan Roesec07f68d2019-07-03 07:22:20 +0200111 mtk_wdt_set_timeout(dev, timeout_ms);
Ryder Lee090543f2018-11-15 10:07:57 +0800112
Stefan Roesec07f68d2019-07-03 07:22:20 +0200113 mtk_wdt_reset(dev);
Shannon Barber2bc18212019-06-07 20:48:19 +0000114
Ryder Lee090543f2018-11-15 10:07:57 +0800115 /* Enable watchdog reset signal */
116 setbits_le32(priv->base + MTK_WDT_MODE,
117 WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN);
118
119 return 0;
120}
121
122static int mtk_wdt_probe(struct udevice *dev)
123{
124 struct mtk_wdt_priv *priv = dev_get_priv(dev);
125
126 priv->base = dev_read_addr_ptr(dev);
127 if (!priv->base)
128 return -ENOENT;
129
130 /* Clear status */
131 clrsetbits_le32(priv->base + MTK_WDT_MODE,
132 WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY);
133
134 return mtk_wdt_stop(dev);
135}
136
137static const struct wdt_ops mtk_wdt_ops = {
138 .start = mtk_wdt_start,
139 .reset = mtk_wdt_reset,
140 .stop = mtk_wdt_stop,
141 .expire_now = mtk_wdt_expire_now,
142};
143
144static const struct udevice_id mtk_wdt_ids[] = {
145 { .compatible = "mediatek,wdt"},
146 {}
147};
148
149U_BOOT_DRIVER(mtk_wdt) = {
150 .name = "mtk_wdt",
151 .id = UCLASS_WDT,
152 .of_match = mtk_wdt_ids,
153 .priv_auto_alloc_size = sizeof(struct mtk_wdt_priv),
154 .probe = mtk_wdt_probe,
155 .ops = &mtk_wdt_ops,
156 .flags = DM_FLAG_PRE_RELOC,
157};