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Chandan Nath5289e832011-10-14 02:58:26 +00001/*
2 * board.c
3 *
4 * Common board functions for AM33XX based boards
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath5289e832011-10-14 02:58:26 +00009 */
10
11#include <common.h>
Simon Glassd12010b2014-10-22 21:37:10 -060012#include <dm.h>
Tom Rini973b6632012-07-30 16:13:10 -070013#include <errno.h>
Simon Glass4119e062014-10-22 21:37:11 -060014#include <ns16550.h>
Tom Rini47f7bca2012-08-13 12:03:19 -070015#include <spl.h>
Chandan Nath5289e832011-10-14 02:58:26 +000016#include <asm/arch/cpu.h>
17#include <asm/arch/hardware.h>
Chandan Nath8a8f0842012-01-09 20:38:59 +000018#include <asm/arch/omap.h>
Chandan Nath5289e832011-10-14 02:58:26 +000019#include <asm/arch/ddr_defs.h>
20#include <asm/arch/clock.h>
Steve Sakoman3b971522012-06-04 05:35:34 +000021#include <asm/arch/gpio.h>
Ilya Yanok8eb16b72012-11-06 13:06:30 +000022#include <asm/arch/mem.h>
Chandan Nath8a8f0842012-01-09 20:38:59 +000023#include <asm/arch/mmc_host_def.h>
Tom Rinidb7dd812012-07-31 10:50:01 -070024#include <asm/arch/sys_proto.h>
Chandan Nath5289e832011-10-14 02:58:26 +000025#include <asm/io.h>
Tom Rinifda35eb2012-07-03 08:51:34 -070026#include <asm/emif.h>
Tom Rini65d750b2012-07-31 08:55:01 -070027#include <asm/gpio.h>
Tom Rini973b6632012-07-30 16:13:10 -070028#include <i2c.h>
29#include <miiphy.h>
30#include <cpsw.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090031#include <linux/errno.h>
Tom Rini6a0d8032013-08-30 16:28:44 -040032#include <linux/compiler.h>
Ilya Yanok7df5cf32012-11-06 13:48:23 +000033#include <linux/usb/ch9.h>
34#include <linux/usb/gadget.h>
35#include <linux/usb/musb.h>
36#include <asm/omap_musb.h>
Tom Rini155d4242013-08-28 09:00:28 -040037#include <asm/davinci_rtc.h>
Chandan Nath5289e832011-10-14 02:58:26 +000038
39DECLARE_GLOBAL_DATA_PTR;
40
Tom Rini75507d52015-12-06 11:09:59 -050041#if !CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glass4119e062014-10-22 21:37:11 -060042static const struct ns16550_platdata am33xx_serial[] = {
Adam Ford2f6ed3b2016-03-07 21:08:49 -060043 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
Tom Rini1480fdf2015-07-31 19:55:08 -040044# ifdef CONFIG_SYS_NS16550_COM2
Adam Ford2f6ed3b2016-03-07 21:08:49 -060045 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
Tom Rini1480fdf2015-07-31 19:55:08 -040046# ifdef CONFIG_SYS_NS16550_COM3
Adam Ford2f6ed3b2016-03-07 21:08:49 -060047 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
48 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
49 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
50 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
Simon Glass4119e062014-10-22 21:37:11 -060051# endif
Tom Rini1480fdf2015-07-31 19:55:08 -040052# endif
Simon Glass4119e062014-10-22 21:37:11 -060053};
54
55U_BOOT_DEVICES(am33xx_uarts) = {
Tom Rini75507d52015-12-06 11:09:59 -050056 { "ns16550_serial", &am33xx_serial[0] },
Simon Glass4119e062014-10-22 21:37:11 -060057# ifdef CONFIG_SYS_NS16550_COM2
Tom Rini75507d52015-12-06 11:09:59 -050058 { "ns16550_serial", &am33xx_serial[1] },
Simon Glass4119e062014-10-22 21:37:11 -060059# ifdef CONFIG_SYS_NS16550_COM3
Tom Rini75507d52015-12-06 11:09:59 -050060 { "ns16550_serial", &am33xx_serial[2] },
61 { "ns16550_serial", &am33xx_serial[3] },
62 { "ns16550_serial", &am33xx_serial[4] },
63 { "ns16550_serial", &am33xx_serial[5] },
Simon Glass4119e062014-10-22 21:37:11 -060064# endif
65# endif
66};
Simon Glass4119e062014-10-22 21:37:11 -060067
Tom Rini90345c92016-01-05 12:17:15 -050068#ifdef CONFIG_DM_GPIO
69static const struct omap_gpio_platdata am33xx_gpio[] = {
70 { 0, AM33XX_GPIO0_BASE },
71 { 1, AM33XX_GPIO1_BASE },
72 { 2, AM33XX_GPIO2_BASE },
73 { 3, AM33XX_GPIO3_BASE },
74#ifdef CONFIG_AM43XX
75 { 4, AM33XX_GPIO4_BASE },
76 { 5, AM33XX_GPIO5_BASE },
77#endif
78};
79
80U_BOOT_DEVICES(am33xx_gpios) = {
81 { "gpio_omap", &am33xx_gpio[0] },
82 { "gpio_omap", &am33xx_gpio[1] },
83 { "gpio_omap", &am33xx_gpio[2] },
84 { "gpio_omap", &am33xx_gpio[3] },
85#ifdef CONFIG_AM43XX
86 { "gpio_omap", &am33xx_gpio[4] },
87 { "gpio_omap", &am33xx_gpio[5] },
88#endif
89};
90#endif
91#endif
Simon Glassd12010b2014-10-22 21:37:10 -060092
Tom Rini1480fdf2015-07-31 19:55:08 -040093#ifndef CONFIG_DM_GPIO
Dave Gerlachcd8341b2014-02-10 11:41:49 -050094static const struct gpio_bank gpio_bank_am33xx[] = {
Tom Rini0a9e3402015-07-31 19:55:09 -040095 { (void *)AM33XX_GPIO0_BASE },
96 { (void *)AM33XX_GPIO1_BASE },
97 { (void *)AM33XX_GPIO2_BASE },
98 { (void *)AM33XX_GPIO3_BASE },
Dave Gerlachcd8341b2014-02-10 11:41:49 -050099#ifdef CONFIG_AM43XX
Tom Rini0a9e3402015-07-31 19:55:09 -0400100 { (void *)AM33XX_GPIO4_BASE },
101 { (void *)AM33XX_GPIO5_BASE },
Dave Gerlachcd8341b2014-02-10 11:41:49 -0500102#endif
Steve Sakoman3b971522012-06-04 05:35:34 +0000103};
104
105const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
Simon Glassd12010b2014-10-22 21:37:10 -0600106#endif
107
Chandan Nath876bdd62012-01-09 20:38:58 +0000108#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
Peter Korsgaard75a23882012-10-18 01:21:10 +0000109int cpu_mmc_init(bd_t *bis)
Chandan Nath876bdd62012-01-09 20:38:58 +0000110{
Tom Rini0689a2e2012-08-08 10:31:08 -0700111 int ret;
Peter Korsgaard75a23882012-10-18 01:21:10 +0000112
Nikita Kiryanove3913f52012-12-03 02:19:47 +0000113 ret = omap_mmc_init(0, 0, 0, -1, -1);
Tom Rini0689a2e2012-08-08 10:31:08 -0700114 if (ret)
115 return ret;
116
Nikita Kiryanove3913f52012-12-03 02:19:47 +0000117 return omap_mmc_init(1, 0, 0, -1, -1);
Chandan Nath876bdd62012-01-09 20:38:58 +0000118}
119#endif
Chandan Nath8a8f0842012-01-09 20:38:59 +0000120
Ilya Yanok7df5cf32012-11-06 13:48:23 +0000121/* AM33XX has two MUSB controllers which can be host or gadget */
Paul Kocialkowski95de1e22015-08-04 17:04:06 +0200122#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
Mugunthan V N19570222016-11-17 14:38:07 +0530123 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
124 (!defined(CONFIG_DM_USB))
Ilya Yanok7df5cf32012-11-06 13:48:23 +0000125static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
126
127/* USB 2.0 PHY Control */
128#define CM_PHY_PWRDN (1 << 0)
129#define CM_PHY_OTG_PWRDN (1 << 1)
130#define OTGVDET_EN (1 << 19)
131#define OTGSESSENDEN (1 << 20)
132
133static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
134{
135 if (on) {
136 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
137 OTGVDET_EN | OTGSESSENDEN);
138 } else {
139 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
140 }
141}
142
143static struct musb_hdrc_config musb_config = {
144 .multipoint = 1,
145 .dyn_fifo = 1,
146 .num_eps = 16,
147 .ram_bits = 12,
148};
149
150#ifdef CONFIG_AM335X_USB0
Mugunthan V N1cac34c2016-11-17 14:38:10 +0530151static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
Ilya Yanok7df5cf32012-11-06 13:48:23 +0000152{
153 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
154}
155
156struct omap_musb_board_data otg0_board_data = {
157 .set_phy_power = am33xx_otg0_set_phy_power,
158};
159
160static struct musb_hdrc_platform_data otg0_plat = {
161 .mode = CONFIG_AM335X_USB0_MODE,
162 .config = &musb_config,
163 .power = 50,
164 .platform_ops = &musb_dsps_ops,
165 .board_data = &otg0_board_data,
166};
167#endif
168
169#ifdef CONFIG_AM335X_USB1
Mugunthan V N1cac34c2016-11-17 14:38:10 +0530170static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
Ilya Yanok7df5cf32012-11-06 13:48:23 +0000171{
172 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
173}
174
175struct omap_musb_board_data otg1_board_data = {
176 .set_phy_power = am33xx_otg1_set_phy_power,
177};
178
179static struct musb_hdrc_platform_data otg1_plat = {
180 .mode = CONFIG_AM335X_USB1_MODE,
181 .config = &musb_config,
182 .power = 50,
183 .platform_ops = &musb_dsps_ops,
184 .board_data = &otg1_board_data,
185};
186#endif
187#endif
188
189int arch_misc_init(void)
190{
Mugunthan V N19570222016-11-17 14:38:07 +0530191#ifndef CONFIG_DM_USB
Ilya Yanok7df5cf32012-11-06 13:48:23 +0000192#ifdef CONFIG_AM335X_USB0
193 musb_register(&otg0_plat, &otg0_board_data,
Matt Porter81df2ba2013-03-15 10:07:02 +0000194 (void *)USB0_OTG_BASE);
Ilya Yanok7df5cf32012-11-06 13:48:23 +0000195#endif
196#ifdef CONFIG_AM335X_USB1
197 musb_register(&otg1_plat, &otg1_board_data,
Matt Porter81df2ba2013-03-15 10:07:02 +0000198 (void *)USB1_OTG_BASE);
Ilya Yanok7df5cf32012-11-06 13:48:23 +0000199#endif
Mugunthan V N3aec2642016-11-17 14:38:09 +0530200#else
201 struct udevice *dev;
202 int ret;
203
204 ret = uclass_first_device(UCLASS_MISC, &dev);
205 if (ret || !dev)
206 return ret;
Mugunthan V Nba7916c2016-11-17 14:38:13 +0530207
208#if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
209 ret = usb_ether_init();
210 if (ret) {
211 error("USB ether init failed\n");
212 return ret;
213 }
214#endif
Mugunthan V N19570222016-11-17 14:38:07 +0530215#endif
Ilya Yanok7df5cf32012-11-06 13:48:23 +0000216 return 0;
217}
Heiko Schocher49f78362013-06-05 07:47:56 +0200218
Tom Rinid0e6d342014-04-09 08:25:57 -0400219#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Tom Rini6a0d8032013-08-30 16:28:44 -0400220/*
Tom Rini196311d2014-05-21 12:57:22 -0400221 * In the case of non-SPL based booting we'll want to call these
222 * functions a tiny bit later as it will require gd to be set and cleared
223 * and that's not true in s_init in this case so we cannot do it there.
224 */
225int board_early_init_f(void)
226{
227 prcm_init();
228 set_mux_conf_regs();
229
230 return 0;
231}
232
233/*
Tom Rini6a0d8032013-08-30 16:28:44 -0400234 * This function is the place to do per-board things such as ramp up the
235 * MPU clock frequency.
236 */
237__weak void am33xx_spl_board_init(void)
238{
Steve Kipisz52f7d842013-08-14 10:51:31 -0400239 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
240 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
Tom Rini6a0d8032013-08-30 16:28:44 -0400241}
242
Heiko Schocher16678eb2013-11-04 14:05:00 +0100243#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
Heiko Schocher06604812013-07-30 10:48:54 +0530244static void rtc32k_enable(void)
Heiko Schocher49f78362013-06-05 07:47:56 +0200245{
Tom Rini155d4242013-08-28 09:00:28 -0400246 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
Heiko Schocher49f78362013-06-05 07:47:56 +0200247
248 /*
249 * Unlock the RTC's registers. For more details please see the
250 * RTC_SS section of the TRM. In order to unlock we need to
251 * write these specific values (keys) in this order.
252 */
Tom Rini155d4242013-08-28 09:00:28 -0400253 writel(RTC_KICK0R_WE, &rtc->kick0r);
254 writel(RTC_KICK1R_WE, &rtc->kick1r);
Heiko Schocher49f78362013-06-05 07:47:56 +0200255
256 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
257 writel((1 << 3) | (1 << 6), &rtc->osc);
258}
Heiko Schocher16678eb2013-11-04 14:05:00 +0100259#endif
Heiko Schocher7ea7f682013-06-04 11:00:57 +0200260
Heiko Schocher06604812013-07-30 10:48:54 +0530261static void uart_soft_reset(void)
Heiko Schocher7ea7f682013-06-04 11:00:57 +0200262{
263 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
264 u32 regval;
265
266 regval = readl(&uart_base->uartsyscfg);
267 regval |= UART_RESET;
268 writel(regval, &uart_base->uartsyscfg);
269 while ((readl(&uart_base->uartsyssts) &
270 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
271 ;
272
273 /* Disable smart idle */
274 regval = readl(&uart_base->uartsyscfg);
275 regval |= UART_SMART_IDLE_EN;
276 writel(regval, &uart_base->uartsyscfg);
277}
Heiko Schocher06604812013-07-30 10:48:54 +0530278
279static void watchdog_disable(void)
280{
281 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
282
283 writel(0xAAAA, &wdtimer->wdtwspr);
284 while (readl(&wdtimer->wdtwwps) != 0x0)
285 ;
286 writel(0x5555, &wdtimer->wdtwspr);
287 while (readl(&wdtimer->wdtwwps) != 0x0)
288 ;
289}
Heiko Schocher06604812013-07-30 10:48:54 +0530290
291void s_init(void)
292{
Lokesh Vutlac704a992016-10-14 10:35:23 +0530293}
294
295void early_system_init(void)
296{
Heiko Schocher06604812013-07-30 10:48:54 +0530297 /*
298 * The ROM will only have set up sufficient pinmux to allow for the
299 * first 4KiB NOR to be read, we must finish doing what we know of
300 * the NOR mux in this space in order to continue.
301 */
302#ifdef CONFIG_NOR_BOOT
303 enable_norboot_pin_mux();
304#endif
Heiko Schocher06604812013-07-30 10:48:54 +0530305 watchdog_disable();
Heiko Schocher06604812013-07-30 10:48:54 +0530306 set_uart_mux_conf();
Lokesh Vutlab64a7cb2016-10-14 10:35:24 +0530307 setup_early_clocks();
Heiko Schocher06604812013-07-30 10:48:54 +0530308 uart_soft_reset();
Lokesh Vutla140d76a2016-10-14 10:35:25 +0530309#ifdef CONFIG_TI_I2C_BOARD_DETECT
310 do_board_detect();
311#endif
Heiko Schocher16678eb2013-11-04 14:05:00 +0100312#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
Heiko Schocher06604812013-07-30 10:48:54 +0530313 /* Enable RTC32K clock */
314 rtc32k_enable();
Heiko Schocher16678eb2013-11-04 14:05:00 +0100315#endif
Heiko Schocher06604812013-07-30 10:48:54 +0530316}
Lokesh Vutlac704a992016-10-14 10:35:23 +0530317
318#ifdef CONFIG_SPL_BUILD
319void board_init_f(ulong dummy)
320{
321 early_system_init();
322 board_early_init_f();
323 sdram_init();
324}
Tom Rinid73f38f2014-03-05 14:57:47 -0500325#endif
Lokesh Vutlac704a992016-10-14 10:35:23 +0530326
327#endif
328
329int arch_cpu_init_dm(void)
330{
331#ifndef CONFIG_SKIP_LOWLEVEL_INIT
332 early_system_init();
333#endif
334 return 0;
335}