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Hans de Goede53ab4af2015-04-15 19:03:49 +02001/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
Hans de Goede53ab4af2015-04-15 19:03:49 +020020 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "skeleton.dtsi"
45
46#include <dt-bindings/thermal/thermal.h>
47
Hans de Goede80e5f832016-03-14 17:37:09 +010048#include <dt-bindings/clock/sun4i-a10-pll2.h>
Hans de Goede53ab4af2015-04-15 19:03:49 +020049#include <dt-bindings/dma/sun4i-a10.h>
50#include <dt-bindings/pinctrl/sun4i-a10.h>
51
52/ {
53 interrupt-parent = <&intc>;
54
55 aliases {
56 ethernet0 = &emac;
57 };
58
59 chosen {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 ranges;
63
64 framebuffer@0 {
Hans de Goede8b1ba942015-06-02 15:53:40 +020065 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer";
Hans de Goede53ab4af2015-04-15 19:03:49 +020067 allwinner,pipeline = "de_be0-lcd0-hdmi";
Hans de Goede860fbdd2016-08-18 20:51:12 +020068 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
69 <&ahb_gates 44>, <&de_be0_clk>,
70 <&tcon0_ch1_clk>, <&dram_gates 26>;
Hans de Goede53ab4af2015-04-15 19:03:49 +020071 status = "disabled";
72 };
73
74 framebuffer@1 {
Hans de Goede8b1ba942015-06-02 15:53:40 +020075 compatible = "allwinner,simple-framebuffer",
76 "simple-framebuffer";
Hans de Goede53ab4af2015-04-15 19:03:49 +020077 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
Hans de Goede860fbdd2016-08-18 20:51:12 +020078 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
Hans de Goede80e5f832016-03-14 17:37:09 +010079 <&ahb_gates 44>, <&ahb_gates 46>,
Hans de Goede860fbdd2016-08-18 20:51:12 +020080 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>,
Hans de Goede80e5f832016-03-14 17:37:09 +010081 <&dram_gates 25>, <&dram_gates 26>;
Hans de Goede53ab4af2015-04-15 19:03:49 +020082 status = "disabled";
83 };
84
85 framebuffer@2 {
86 compatible = "allwinner,simple-framebuffer",
87 "simple-framebuffer";
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
Hans de Goede860fbdd2016-08-18 20:51:12 +020089 clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>,
90 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,
91 <&dram_gates 25>, <&dram_gates 26>;
Hans de Goede53ab4af2015-04-15 19:03:49 +020092 status = "disabled";
93 };
94
95 framebuffer@3 {
96 compatible = "allwinner,simple-framebuffer",
97 "simple-framebuffer";
98 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
Hans de Goede860fbdd2016-08-18 20:51:12 +020099 clocks = <&ahb_gates 34>, <&ahb_gates 36>,
Hans de Goede80e5f832016-03-14 17:37:09 +0100100 <&ahb_gates 44>, <&ahb_gates 46>,
Hans de Goede860fbdd2016-08-18 20:51:12 +0200101 <&de_be0_clk>, <&de_fe0_clk>,
102 <&tcon0_ch1_clk>, <&dram_gates 5>,
Hans de Goede80e5f832016-03-14 17:37:09 +0100103 <&dram_gates 25>, <&dram_gates 26>;
Hans de Goede53ab4af2015-04-15 19:03:49 +0200104 status = "disabled";
105 };
106 };
107
108 cpus {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 cpu0: cpu@0 {
112 device_type = "cpu";
113 compatible = "arm,cortex-a8";
114 reg = <0x0>;
115 clocks = <&cpu>;
116 clock-latency = <244144>; /* 8 32k periods */
117 operating-points = <
Hans de Goede8b1ba942015-06-02 15:53:40 +0200118 /* kHz uV */
Hans de Goede53ab4af2015-04-15 19:03:49 +0200119 1008000 1400000
Hans de Goede8b1ba942015-06-02 15:53:40 +0200120 912000 1350000
121 864000 1300000
122 624000 1250000
Hans de Goede53ab4af2015-04-15 19:03:49 +0200123 >;
124 #cooling-cells = <2>;
125 cooling-min-level = <0>;
126 cooling-max-level = <3>;
127 };
128 };
129
130 thermal-zones {
131 cpu_thermal {
132 /* milliseconds */
133 polling-delay-passive = <250>;
134 polling-delay = <1000>;
135 thermal-sensors = <&rtp>;
136
137 cooling-maps {
138 map0 {
139 trip = <&cpu_alert0>;
140 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
141 };
142 };
143
144 trips {
145 cpu_alert0: cpu_alert0 {
146 /* milliCelsius */
147 temperature = <850000>;
148 hysteresis = <2000>;
149 type = "passive";
150 };
151
152 cpu_crit: cpu_crit {
153 /* milliCelsius */
154 temperature = <100000>;
155 hysteresis = <2000>;
156 type = "critical";
157 };
158 };
159 };
160 };
161
162 memory {
163 reg = <0x40000000 0x80000000>;
164 };
165
166 clocks {
167 #address-cells = <1>;
168 #size-cells = <1>;
169 ranges;
170
171 /*
172 * This is a dummy clock, to be used as placeholder on
173 * other mux clocks when a specific parent clock is not
174 * yet implemented. It should be dropped when the driver
175 * is complete.
176 */
177 dummy: dummy {
178 #clock-cells = <0>;
179 compatible = "fixed-clock";
180 clock-frequency = <0>;
181 };
182
183 osc24M: clk@01c20050 {
184 #clock-cells = <0>;
185 compatible = "allwinner,sun4i-a10-osc-clk";
186 reg = <0x01c20050 0x4>;
187 clock-frequency = <24000000>;
188 clock-output-names = "osc24M";
189 };
190
Hans de Goede860fbdd2016-08-18 20:51:12 +0200191 osc3M: osc3M_clk {
192 compatible = "fixed-factor-clock";
193 #clock-cells = <0>;
194 clock-div = <8>;
195 clock-mult = <1>;
196 clocks = <&osc24M>;
197 clock-output-names = "osc3M";
198 };
199
Hans de Goede53ab4af2015-04-15 19:03:49 +0200200 osc32k: clk@0 {
201 #clock-cells = <0>;
202 compatible = "fixed-clock";
203 clock-frequency = <32768>;
204 clock-output-names = "osc32k";
205 };
206
207 pll1: clk@01c20000 {
208 #clock-cells = <0>;
209 compatible = "allwinner,sun4i-a10-pll1-clk";
210 reg = <0x01c20000 0x4>;
211 clocks = <&osc24M>;
212 clock-output-names = "pll1";
213 };
214
Hans de Goede80e5f832016-03-14 17:37:09 +0100215 pll2: clk@01c20008 {
216 #clock-cells = <1>;
217 compatible = "allwinner,sun4i-a10-pll2-clk";
218 reg = <0x01c20008 0x8>;
219 clocks = <&osc24M>;
220 clock-output-names = "pll2-1x", "pll2-2x",
221 "pll2-4x", "pll2-8x";
222 };
223
Hans de Goede860fbdd2016-08-18 20:51:12 +0200224 pll3: clk@01c20010 {
225 #clock-cells = <0>;
226 compatible = "allwinner,sun4i-a10-pll3-clk";
227 reg = <0x01c20010 0x4>;
228 clocks = <&osc3M>;
229 clock-output-names = "pll3";
230 };
231
232 pll3x2: pll3x2_clk {
233 compatible = "fixed-factor-clock";
234 #clock-cells = <0>;
235 clock-div = <1>;
236 clock-mult = <2>;
237 clocks = <&pll3>;
238 clock-output-names = "pll3-2x";
239 };
240
Hans de Goede53ab4af2015-04-15 19:03:49 +0200241 pll4: clk@01c20018 {
242 #clock-cells = <0>;
243 compatible = "allwinner,sun4i-a10-pll1-clk";
244 reg = <0x01c20018 0x4>;
245 clocks = <&osc24M>;
246 clock-output-names = "pll4";
247 };
248
249 pll5: clk@01c20020 {
250 #clock-cells = <1>;
251 compatible = "allwinner,sun4i-a10-pll5-clk";
252 reg = <0x01c20020 0x4>;
253 clocks = <&osc24M>;
254 clock-output-names = "pll5_ddr", "pll5_other";
255 };
256
257 pll6: clk@01c20028 {
258 #clock-cells = <1>;
259 compatible = "allwinner,sun4i-a10-pll6-clk";
260 reg = <0x01c20028 0x4>;
261 clocks = <&osc24M>;
262 clock-output-names = "pll6_sata", "pll6_other", "pll6";
263 };
264
Hans de Goede860fbdd2016-08-18 20:51:12 +0200265 pll7: clk@01c20030 {
266 #clock-cells = <0>;
267 compatible = "allwinner,sun4i-a10-pll3-clk";
268 reg = <0x01c20030 0x4>;
269 clocks = <&osc3M>;
270 clock-output-names = "pll7";
271 };
272
273 pll7x2: pll7x2_clk {
274 compatible = "fixed-factor-clock";
275 #clock-cells = <0>;
276 clock-div = <1>;
277 clock-mult = <2>;
278 clocks = <&pll7>;
279 clock-output-names = "pll7-2x";
280 };
281
Hans de Goede53ab4af2015-04-15 19:03:49 +0200282 /* dummy is 200M */
283 cpu: cpu@01c20054 {
284 #clock-cells = <0>;
285 compatible = "allwinner,sun4i-a10-cpu-clk";
286 reg = <0x01c20054 0x4>;
287 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
288 clock-output-names = "cpu";
289 };
290
291 axi: axi@01c20054 {
292 #clock-cells = <0>;
293 compatible = "allwinner,sun4i-a10-axi-clk";
294 reg = <0x01c20054 0x4>;
295 clocks = <&cpu>;
296 clock-output-names = "axi";
297 };
298
299 axi_gates: clk@01c2005c {
300 #clock-cells = <1>;
301 compatible = "allwinner,sun4i-a10-axi-gates-clk";
302 reg = <0x01c2005c 0x4>;
303 clocks = <&axi>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100304 clock-indices = <0>;
Hans de Goede53ab4af2015-04-15 19:03:49 +0200305 clock-output-names = "axi_dram";
306 };
307
308 ahb: ahb@01c20054 {
309 #clock-cells = <0>;
310 compatible = "allwinner,sun4i-a10-ahb-clk";
311 reg = <0x01c20054 0x4>;
312 clocks = <&axi>;
313 clock-output-names = "ahb";
314 };
315
316 ahb_gates: clk@01c20060 {
317 #clock-cells = <1>;
318 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
319 reg = <0x01c20060 0x8>;
320 clocks = <&ahb>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100321 clock-indices = <0>, <1>,
322 <2>, <3>,
323 <4>, <5>, <6>,
324 <7>, <8>, <9>,
325 <10>, <11>, <12>,
326 <13>, <14>, <16>,
327 <17>, <18>, <20>,
328 <21>, <22>, <23>,
329 <24>, <25>, <26>,
330 <32>, <33>, <34>,
331 <35>, <36>, <37>,
332 <40>, <41>, <43>,
333 <44>, <45>,
334 <46>, <47>,
335 <50>, <52>;
Hans de Goede53ab4af2015-04-15 19:03:49 +0200336 clock-output-names = "ahb_usb0", "ahb_ehci0",
Hans de Goede80e5f832016-03-14 17:37:09 +0100337 "ahb_ohci0", "ahb_ehci1",
338 "ahb_ohci1", "ahb_ss", "ahb_dma",
339 "ahb_bist", "ahb_mmc0", "ahb_mmc1",
340 "ahb_mmc2", "ahb_mmc3", "ahb_ms",
341 "ahb_nand", "ahb_sdram", "ahb_ace",
342 "ahb_emac", "ahb_ts", "ahb_spi0",
343 "ahb_spi1", "ahb_spi2", "ahb_spi3",
344 "ahb_pata", "ahb_sata", "ahb_gps",
345 "ahb_ve", "ahb_tvd", "ahb_tve0",
346 "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
347 "ahb_csi0", "ahb_csi1", "ahb_hdmi",
348 "ahb_de_be0", "ahb_de_be1",
349 "ahb_de_fe0", "ahb_de_fe1",
350 "ahb_mp", "ahb_mali400";
Hans de Goede53ab4af2015-04-15 19:03:49 +0200351 };
352
353 apb0: apb0@01c20054 {
354 #clock-cells = <0>;
355 compatible = "allwinner,sun4i-a10-apb0-clk";
356 reg = <0x01c20054 0x4>;
357 clocks = <&ahb>;
358 clock-output-names = "apb0";
359 };
360
361 apb0_gates: clk@01c20068 {
362 #clock-cells = <1>;
363 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
364 reg = <0x01c20068 0x4>;
365 clocks = <&apb0>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100366 clock-indices = <0>, <1>,
367 <2>, <3>,
368 <5>, <6>,
369 <7>, <10>;
Hans de Goede53ab4af2015-04-15 19:03:49 +0200370 clock-output-names = "apb0_codec", "apb0_spdif",
Hans de Goede80e5f832016-03-14 17:37:09 +0100371 "apb0_ac97", "apb0_iis",
372 "apb0_pio", "apb0_ir0",
373 "apb0_ir1", "apb0_keypad";
Hans de Goede53ab4af2015-04-15 19:03:49 +0200374 };
375
376 apb1: clk@01c20058 {
377 #clock-cells = <0>;
378 compatible = "allwinner,sun4i-a10-apb1-clk";
379 reg = <0x01c20058 0x4>;
380 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
381 clock-output-names = "apb1";
382 };
383
384 apb1_gates: clk@01c2006c {
385 #clock-cells = <1>;
386 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
387 reg = <0x01c2006c 0x4>;
388 clocks = <&apb1>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100389 clock-indices = <0>, <1>,
390 <2>, <4>,
391 <5>, <6>,
392 <7>, <16>,
393 <17>, <18>,
394 <19>, <20>,
395 <21>, <22>,
396 <23>;
Hans de Goede53ab4af2015-04-15 19:03:49 +0200397 clock-output-names = "apb1_i2c0", "apb1_i2c1",
Hans de Goede80e5f832016-03-14 17:37:09 +0100398 "apb1_i2c2", "apb1_can",
399 "apb1_scr", "apb1_ps20",
400 "apb1_ps21", "apb1_uart0",
401 "apb1_uart1", "apb1_uart2",
402 "apb1_uart3", "apb1_uart4",
403 "apb1_uart5", "apb1_uart6",
404 "apb1_uart7";
Hans de Goede53ab4af2015-04-15 19:03:49 +0200405 };
406
407 nand_clk: clk@01c20080 {
408 #clock-cells = <0>;
409 compatible = "allwinner,sun4i-a10-mod0-clk";
410 reg = <0x01c20080 0x4>;
411 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
412 clock-output-names = "nand";
413 };
414
415 ms_clk: clk@01c20084 {
416 #clock-cells = <0>;
417 compatible = "allwinner,sun4i-a10-mod0-clk";
418 reg = <0x01c20084 0x4>;
419 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
420 clock-output-names = "ms";
421 };
422
423 mmc0_clk: clk@01c20088 {
424 #clock-cells = <1>;
425 compatible = "allwinner,sun4i-a10-mmc-clk";
426 reg = <0x01c20088 0x4>;
427 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
428 clock-output-names = "mmc0",
429 "mmc0_output",
430 "mmc0_sample";
431 };
432
433 mmc1_clk: clk@01c2008c {
434 #clock-cells = <1>;
435 compatible = "allwinner,sun4i-a10-mmc-clk";
436 reg = <0x01c2008c 0x4>;
437 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
438 clock-output-names = "mmc1",
439 "mmc1_output",
440 "mmc1_sample";
441 };
442
443 mmc2_clk: clk@01c20090 {
444 #clock-cells = <1>;
445 compatible = "allwinner,sun4i-a10-mmc-clk";
446 reg = <0x01c20090 0x4>;
447 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
448 clock-output-names = "mmc2",
449 "mmc2_output",
450 "mmc2_sample";
451 };
452
453 mmc3_clk: clk@01c20094 {
454 #clock-cells = <1>;
455 compatible = "allwinner,sun4i-a10-mmc-clk";
456 reg = <0x01c20094 0x4>;
457 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
458 clock-output-names = "mmc3",
459 "mmc3_output",
460 "mmc3_sample";
461 };
462
463 ts_clk: clk@01c20098 {
464 #clock-cells = <0>;
465 compatible = "allwinner,sun4i-a10-mod0-clk";
466 reg = <0x01c20098 0x4>;
467 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
468 clock-output-names = "ts";
469 };
470
471 ss_clk: clk@01c2009c {
472 #clock-cells = <0>;
473 compatible = "allwinner,sun4i-a10-mod0-clk";
474 reg = <0x01c2009c 0x4>;
475 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
476 clock-output-names = "ss";
477 };
478
479 spi0_clk: clk@01c200a0 {
480 #clock-cells = <0>;
481 compatible = "allwinner,sun4i-a10-mod0-clk";
482 reg = <0x01c200a0 0x4>;
483 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
484 clock-output-names = "spi0";
485 };
486
487 spi1_clk: clk@01c200a4 {
488 #clock-cells = <0>;
489 compatible = "allwinner,sun4i-a10-mod0-clk";
490 reg = <0x01c200a4 0x4>;
491 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
492 clock-output-names = "spi1";
493 };
494
495 spi2_clk: clk@01c200a8 {
496 #clock-cells = <0>;
497 compatible = "allwinner,sun4i-a10-mod0-clk";
498 reg = <0x01c200a8 0x4>;
499 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
500 clock-output-names = "spi2";
501 };
502
503 pata_clk: clk@01c200ac {
504 #clock-cells = <0>;
505 compatible = "allwinner,sun4i-a10-mod0-clk";
506 reg = <0x01c200ac 0x4>;
507 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
508 clock-output-names = "pata";
509 };
510
511 ir0_clk: clk@01c200b0 {
512 #clock-cells = <0>;
513 compatible = "allwinner,sun4i-a10-mod0-clk";
514 reg = <0x01c200b0 0x4>;
515 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
516 clock-output-names = "ir0";
517 };
518
519 ir1_clk: clk@01c200b4 {
520 #clock-cells = <0>;
521 compatible = "allwinner,sun4i-a10-mod0-clk";
522 reg = <0x01c200b4 0x4>;
523 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
524 clock-output-names = "ir1";
525 };
526
Hans de Goede860fbdd2016-08-18 20:51:12 +0200527 spdif_clk: clk@01c200c0 {
528 #clock-cells = <0>;
529 compatible = "allwinner,sun4i-a10-mod1-clk";
530 reg = <0x01c200c0 0x4>;
531 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
532 <&pll2 SUN4I_A10_PLL2_4X>,
533 <&pll2 SUN4I_A10_PLL2_2X>,
534 <&pll2 SUN4I_A10_PLL2_1X>;
535 clock-output-names = "spdif";
536 };
537
Hans de Goede53ab4af2015-04-15 19:03:49 +0200538 usb_clk: clk@01c200cc {
539 #clock-cells = <1>;
Hans de Goede8b1ba942015-06-02 15:53:40 +0200540 #reset-cells = <1>;
Hans de Goede53ab4af2015-04-15 19:03:49 +0200541 compatible = "allwinner,sun4i-a10-usb-clk";
542 reg = <0x01c200cc 0x4>;
543 clocks = <&pll6 1>;
Hans de Goede8b1ba942015-06-02 15:53:40 +0200544 clock-output-names = "usb_ohci0", "usb_ohci1",
545 "usb_phy";
Hans de Goede53ab4af2015-04-15 19:03:49 +0200546 };
547
548 spi3_clk: clk@01c200d4 {
549 #clock-cells = <0>;
550 compatible = "allwinner,sun4i-a10-mod0-clk";
551 reg = <0x01c200d4 0x4>;
552 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
553 clock-output-names = "spi3";
554 };
Hans de Goede80e5f832016-03-14 17:37:09 +0100555
556 dram_gates: clk@01c20100 {
557 #clock-cells = <1>;
558 compatible = "allwinner,sun4i-a10-dram-gates-clk";
559 reg = <0x01c20100 0x4>;
560 clocks = <&pll5 0>;
561 clock-indices = <0>,
562 <1>, <2>,
563 <3>,
564 <4>,
565 <5>, <6>,
566 <15>,
567 <24>, <25>,
568 <26>, <27>,
569 <28>, <29>;
570 clock-output-names = "dram_ve",
571 "dram_csi0", "dram_csi1",
572 "dram_ts",
573 "dram_tvd",
574 "dram_tve0", "dram_tve1",
575 "dram_output",
576 "dram_de_fe1", "dram_de_fe0",
577 "dram_de_be0", "dram_de_be1",
578 "dram_de_mp", "dram_ace";
579 };
580
Hans de Goede860fbdd2016-08-18 20:51:12 +0200581 de_be0_clk: clk@01c20104 {
582 #clock-cells = <0>;
583 #reset-cells = <0>;
584 compatible = "allwinner,sun4i-a10-display-clk";
585 reg = <0x01c20104 0x4>;
586 clocks = <&pll3>, <&pll7>, <&pll5 1>;
587 clock-output-names = "de-be0";
588 };
589
590 de_be1_clk: clk@01c20108 {
591 #clock-cells = <0>;
592 #reset-cells = <0>;
593 compatible = "allwinner,sun4i-a10-display-clk";
594 reg = <0x01c20108 0x4>;
595 clocks = <&pll3>, <&pll7>, <&pll5 1>;
596 clock-output-names = "de-be1";
597 };
598
599 de_fe0_clk: clk@01c2010c {
600 #clock-cells = <0>;
601 #reset-cells = <0>;
602 compatible = "allwinner,sun4i-a10-display-clk";
603 reg = <0x01c2010c 0x4>;
604 clocks = <&pll3>, <&pll7>, <&pll5 1>;
605 clock-output-names = "de-fe0";
606 };
607
608 de_fe1_clk: clk@01c20110 {
609 #clock-cells = <0>;
610 #reset-cells = <0>;
611 compatible = "allwinner,sun4i-a10-display-clk";
612 reg = <0x01c20110 0x4>;
613 clocks = <&pll3>, <&pll7>, <&pll5 1>;
614 clock-output-names = "de-fe1";
615 };
616
617
618 tcon0_ch0_clk: clk@01c20118 {
619 #clock-cells = <0>;
620 #reset-cells = <1>;
621 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
622 reg = <0x01c20118 0x4>;
623 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
624 clock-output-names = "tcon0-ch0-sclk";
625
626 };
627
628 tcon1_ch0_clk: clk@01c2011c {
629 #clock-cells = <0>;
630 #reset-cells = <1>;
631 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
632 reg = <0x01c2011c 0x4>;
633 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
634 clock-output-names = "tcon1-ch0-sclk";
635
636 };
637
638 tcon0_ch1_clk: clk@01c2012c {
639 #clock-cells = <0>;
640 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
641 reg = <0x01c2012c 0x4>;
642 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
643 clock-output-names = "tcon0-ch1-sclk";
644
645 };
646
647 tcon1_ch1_clk: clk@01c20130 {
648 #clock-cells = <0>;
649 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
650 reg = <0x01c20130 0x4>;
651 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
652 clock-output-names = "tcon1-ch1-sclk";
653
654 };
655
Hans de Goede80e5f832016-03-14 17:37:09 +0100656 ve_clk: clk@01c2013c {
657 #clock-cells = <0>;
658 #reset-cells = <0>;
659 compatible = "allwinner,sun4i-a10-ve-clk";
660 reg = <0x01c2013c 0x4>;
661 clocks = <&pll4>;
662 clock-output-names = "ve";
663 };
664
665 codec_clk: clk@01c20140 {
666 #clock-cells = <0>;
667 compatible = "allwinner,sun4i-a10-codec-clk";
668 reg = <0x01c20140 0x4>;
669 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
670 clock-output-names = "codec";
671 };
Hans de Goede53ab4af2015-04-15 19:03:49 +0200672 };
673
Hans de Goede53ab4af2015-04-15 19:03:49 +0200674 soc@01c00000 {
675 compatible = "simple-bus";
676 #address-cells = <1>;
677 #size-cells = <1>;
678 ranges;
679
Hans de Goede53ab4af2015-04-15 19:03:49 +0200680 sram-controller@01c00000 {
681 compatible = "allwinner,sun4i-a10-sram-controller";
682 reg = <0x01c00000 0x30>;
Hans de Goede8b1ba942015-06-02 15:53:40 +0200683 #address-cells = <1>;
684 #size-cells = <1>;
685 ranges;
686
687 sram_a: sram@00000000 {
688 compatible = "mmio-sram";
689 reg = <0x00000000 0xc000>;
690 #address-cells = <1>;
691 #size-cells = <1>;
692 ranges = <0 0x00000000 0xc000>;
693
694 emac_sram: sram-section@8000 {
695 compatible = "allwinner,sun4i-a10-sram-a3-a4";
696 reg = <0x8000 0x4000>;
697 status = "disabled";
698 };
699 };
700
701 sram_d: sram@00010000 {
702 compatible = "mmio-sram";
703 reg = <0x00010000 0x1000>;
704 #address-cells = <1>;
705 #size-cells = <1>;
706 ranges = <0 0x00010000 0x1000>;
707
708 otg_sram: sram-section@0000 {
709 compatible = "allwinner,sun4i-a10-sram-d";
710 reg = <0x0000 0x1000>;
711 status = "disabled";
712 };
713 };
Hans de Goede53ab4af2015-04-15 19:03:49 +0200714 };
715
716 dma: dma-controller@01c02000 {
717 compatible = "allwinner,sun4i-a10-dma";
718 reg = <0x01c02000 0x1000>;
719 interrupts = <27>;
720 clocks = <&ahb_gates 6>;
721 #dma-cells = <2>;
722 };
723
Hans de Goede860fbdd2016-08-18 20:51:12 +0200724 nfc: nand@01c03000 {
725 compatible = "allwinner,sun4i-a10-nand";
726 reg = <0x01c03000 0x1000>;
727 interrupts = <37>;
728 clocks = <&ahb_gates 13>, <&nand_clk>;
729 clock-names = "ahb", "mod";
730 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
731 dma-names = "rxtx";
732 status = "disabled";
733 #address-cells = <1>;
734 #size-cells = <0>;
735 };
736
Hans de Goede53ab4af2015-04-15 19:03:49 +0200737 spi0: spi@01c05000 {
738 compatible = "allwinner,sun4i-a10-spi";
739 reg = <0x01c05000 0x1000>;
740 interrupts = <10>;
741 clocks = <&ahb_gates 20>, <&spi0_clk>;
742 clock-names = "ahb", "mod";
743 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
744 <&dma SUN4I_DMA_DEDICATED 26>;
745 dma-names = "rx", "tx";
746 status = "disabled";
747 #address-cells = <1>;
748 #size-cells = <0>;
749 };
750
751 spi1: spi@01c06000 {
752 compatible = "allwinner,sun4i-a10-spi";
753 reg = <0x01c06000 0x1000>;
754 interrupts = <11>;
755 clocks = <&ahb_gates 21>, <&spi1_clk>;
756 clock-names = "ahb", "mod";
757 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
758 <&dma SUN4I_DMA_DEDICATED 8>;
759 dma-names = "rx", "tx";
760 status = "disabled";
761 #address-cells = <1>;
762 #size-cells = <0>;
763 };
764
765 emac: ethernet@01c0b000 {
766 compatible = "allwinner,sun4i-a10-emac";
767 reg = <0x01c0b000 0x1000>;
768 interrupts = <55>;
769 clocks = <&ahb_gates 17>;
Hans de Goede8b1ba942015-06-02 15:53:40 +0200770 allwinner,sram = <&emac_sram 1>;
Hans de Goede53ab4af2015-04-15 19:03:49 +0200771 status = "disabled";
772 };
773
774 mdio: mdio@01c0b080 {
775 compatible = "allwinner,sun4i-a10-mdio";
776 reg = <0x01c0b080 0x14>;
777 status = "disabled";
778 #address-cells = <1>;
779 #size-cells = <0>;
780 };
781
782 mmc0: mmc@01c0f000 {
783 compatible = "allwinner,sun4i-a10-mmc";
784 reg = <0x01c0f000 0x1000>;
785 clocks = <&ahb_gates 8>,
786 <&mmc0_clk 0>,
787 <&mmc0_clk 1>,
788 <&mmc0_clk 2>;
789 clock-names = "ahb",
790 "mmc",
791 "output",
792 "sample";
793 interrupts = <32>;
794 status = "disabled";
795 #address-cells = <1>;
796 #size-cells = <0>;
797 };
798
799 mmc1: mmc@01c10000 {
800 compatible = "allwinner,sun4i-a10-mmc";
801 reg = <0x01c10000 0x1000>;
802 clocks = <&ahb_gates 9>,
803 <&mmc1_clk 0>,
804 <&mmc1_clk 1>,
805 <&mmc1_clk 2>;
806 clock-names = "ahb",
807 "mmc",
808 "output",
809 "sample";
810 interrupts = <33>;
811 status = "disabled";
812 #address-cells = <1>;
813 #size-cells = <0>;
814 };
815
816 mmc2: mmc@01c11000 {
817 compatible = "allwinner,sun4i-a10-mmc";
818 reg = <0x01c11000 0x1000>;
819 clocks = <&ahb_gates 10>,
820 <&mmc2_clk 0>,
821 <&mmc2_clk 1>,
822 <&mmc2_clk 2>;
823 clock-names = "ahb",
824 "mmc",
825 "output",
826 "sample";
827 interrupts = <34>;
828 status = "disabled";
829 #address-cells = <1>;
830 #size-cells = <0>;
831 };
832
833 mmc3: mmc@01c12000 {
834 compatible = "allwinner,sun4i-a10-mmc";
835 reg = <0x01c12000 0x1000>;
836 clocks = <&ahb_gates 11>,
837 <&mmc3_clk 0>,
838 <&mmc3_clk 1>,
839 <&mmc3_clk 2>;
840 clock-names = "ahb",
841 "mmc",
842 "output",
843 "sample";
844 interrupts = <35>;
845 status = "disabled";
846 #address-cells = <1>;
847 #size-cells = <0>;
848 };
849
Hans de Goededa52a4a2015-08-05 17:39:14 +0200850 usb_otg: usb@01c13000 {
851 compatible = "allwinner,sun4i-a10-musb";
852 reg = <0x01c13000 0x0400>;
853 clocks = <&ahb_gates 0>;
854 interrupts = <38>;
855 interrupt-names = "mc";
856 phys = <&usbphy 0>;
857 phy-names = "usb";
858 extcon = <&usbphy 0>;
859 allwinner,sram = <&otg_sram 1>;
860 status = "disabled";
861 };
862
Hans de Goede53ab4af2015-04-15 19:03:49 +0200863 usbphy: phy@01c13400 {
864 #phy-cells = <1>;
865 compatible = "allwinner,sun4i-a10-usb-phy";
866 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
867 reg-names = "phy_ctrl", "pmu1", "pmu2";
868 clocks = <&usb_clk 8>;
869 clock-names = "usb_phy";
870 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
871 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
872 status = "disabled";
873 };
874
875 ehci0: usb@01c14000 {
876 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
877 reg = <0x01c14000 0x100>;
878 interrupts = <39>;
879 clocks = <&ahb_gates 1>;
880 phys = <&usbphy 1>;
881 phy-names = "usb";
882 status = "disabled";
883 };
884
885 ohci0: usb@01c14400 {
886 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
887 reg = <0x01c14400 0x100>;
888 interrupts = <64>;
889 clocks = <&usb_clk 6>, <&ahb_gates 2>;
890 phys = <&usbphy 1>;
891 phy-names = "usb";
892 status = "disabled";
893 };
894
Hans de Goede80e5f832016-03-14 17:37:09 +0100895 crypto: crypto-engine@01c15000 {
896 compatible = "allwinner,sun4i-a10-crypto";
897 reg = <0x01c15000 0x1000>;
898 interrupts = <86>;
899 clocks = <&ahb_gates 5>, <&ss_clk>;
900 clock-names = "ahb", "mod";
901 };
902
Hans de Goede53ab4af2015-04-15 19:03:49 +0200903 spi2: spi@01c17000 {
904 compatible = "allwinner,sun4i-a10-spi";
905 reg = <0x01c17000 0x1000>;
906 interrupts = <12>;
907 clocks = <&ahb_gates 22>, <&spi2_clk>;
908 clock-names = "ahb", "mod";
909 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
910 <&dma SUN4I_DMA_DEDICATED 28>;
911 dma-names = "rx", "tx";
912 status = "disabled";
913 #address-cells = <1>;
914 #size-cells = <0>;
915 };
916
917 ahci: sata@01c18000 {
918 compatible = "allwinner,sun4i-a10-ahci";
919 reg = <0x01c18000 0x1000>;
920 interrupts = <56>;
921 clocks = <&pll6 0>, <&ahb_gates 25>;
922 status = "disabled";
923 };
924
925 ehci1: usb@01c1c000 {
926 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
927 reg = <0x01c1c000 0x100>;
928 interrupts = <40>;
929 clocks = <&ahb_gates 3>;
930 phys = <&usbphy 2>;
931 phy-names = "usb";
932 status = "disabled";
933 };
934
935 ohci1: usb@01c1c400 {
936 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
937 reg = <0x01c1c400 0x100>;
938 interrupts = <65>;
939 clocks = <&usb_clk 7>, <&ahb_gates 4>;
940 phys = <&usbphy 2>;
941 phy-names = "usb";
942 status = "disabled";
943 };
944
945 spi3: spi@01c1f000 {
946 compatible = "allwinner,sun4i-a10-spi";
947 reg = <0x01c1f000 0x1000>;
948 interrupts = <50>;
949 clocks = <&ahb_gates 23>, <&spi3_clk>;
950 clock-names = "ahb", "mod";
951 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
952 <&dma SUN4I_DMA_DEDICATED 30>;
953 dma-names = "rx", "tx";
954 status = "disabled";
955 #address-cells = <1>;
956 #size-cells = <0>;
957 };
958
959 intc: interrupt-controller@01c20400 {
960 compatible = "allwinner,sun4i-a10-ic";
961 reg = <0x01c20400 0x400>;
962 interrupt-controller;
963 #interrupt-cells = <1>;
964 };
965
966 pio: pinctrl@01c20800 {
967 compatible = "allwinner,sun4i-a10-pinctrl";
968 reg = <0x01c20800 0x400>;
969 interrupts = <28>;
970 clocks = <&apb0_gates 5>;
971 gpio-controller;
972 interrupt-controller;
Hans de Goededa52a4a2015-08-05 17:39:14 +0200973 #interrupt-cells = <3>;
Hans de Goede53ab4af2015-04-15 19:03:49 +0200974 #gpio-cells = <3>;
975
Hans de Goede860fbdd2016-08-18 20:51:12 +0200976 emac_pins_a: emac0@0 {
977 allwinner,pins = "PA0", "PA1", "PA2",
978 "PA3", "PA4", "PA5", "PA6",
979 "PA7", "PA8", "PA9", "PA10",
980 "PA11", "PA12", "PA13", "PA14",
981 "PA15", "PA16";
982 allwinner,function = "emac";
Hans de Goede53ab4af2015-04-15 19:03:49 +0200983 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
984 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
985 };
986
987 i2c0_pins_a: i2c0@0 {
988 allwinner,pins = "PB0", "PB1";
989 allwinner,function = "i2c0";
990 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
991 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
992 };
993
994 i2c1_pins_a: i2c1@0 {
995 allwinner,pins = "PB18", "PB19";
996 allwinner,function = "i2c1";
997 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
998 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
999 };
1000
1001 i2c2_pins_a: i2c2@0 {
1002 allwinner,pins = "PB20", "PB21";
1003 allwinner,function = "i2c2";
1004 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1005 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1006 };
1007
Hans de Goede8b1ba942015-06-02 15:53:40 +02001008 ir0_rx_pins_a: ir0@0 {
1009 allwinner,pins = "PB4";
Hans de Goede53ab4af2015-04-15 19:03:49 +02001010 allwinner,function = "ir0";
1011 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1012 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1013 };
1014
Hans de Goede8b1ba942015-06-02 15:53:40 +02001015 ir0_tx_pins_a: ir0@1 {
1016 allwinner,pins = "PB3";
1017 allwinner,function = "ir0";
1018 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1019 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1020 };
1021
1022 ir1_rx_pins_a: ir1@0 {
1023 allwinner,pins = "PB23";
1024 allwinner,function = "ir1";
1025 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1026 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1027 };
1028
1029 ir1_tx_pins_a: ir1@1 {
1030 allwinner,pins = "PB22";
Hans de Goede53ab4af2015-04-15 19:03:49 +02001031 allwinner,function = "ir1";
1032 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1033 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1034 };
1035
Hans de Goede860fbdd2016-08-18 20:51:12 +02001036 mmc0_pins_a: mmc0@0 {
1037 allwinner,pins = "PF0", "PF1", "PF2",
1038 "PF3", "PF4", "PF5";
1039 allwinner,function = "mmc0";
1040 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1041 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1042 };
1043
1044 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1045 allwinner,pins = "PH1";
1046 allwinner,function = "gpio_in";
1047 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1048 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1049 };
1050
1051 ps20_pins_a: ps20@0 {
1052 allwinner,pins = "PI20", "PI21";
1053 allwinner,function = "ps2";
1054 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1055 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1056 };
1057
1058 ps21_pins_a: ps21@0 {
1059 allwinner,pins = "PH12", "PH13";
1060 allwinner,function = "ps2";
1061 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1062 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1063 };
1064
1065 pwm0_pins_a: pwm0@0 {
1066 allwinner,pins = "PB2";
1067 allwinner,function = "pwm";
1068 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1069 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1070 };
1071
1072 pwm1_pins_a: pwm1@0 {
1073 allwinner,pins = "PI3";
1074 allwinner,function = "pwm";
1075 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1076 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1077 };
1078
1079 spdif_tx_pins_a: spdif@0 {
1080 allwinner,pins = "PB13";
1081 allwinner,function = "spdif";
1082 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1083 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1084 };
1085
Hans de Goede53ab4af2015-04-15 19:03:49 +02001086 spi0_pins_a: spi0@0 {
Hans de Goede8b1ba942015-06-02 15:53:40 +02001087 allwinner,pins = "PI11", "PI12", "PI13";
1088 allwinner,function = "spi0";
1089 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1090 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1091 };
1092
1093 spi0_cs0_pins_a: spi0_cs0@0 {
1094 allwinner,pins = "PI10";
Hans de Goede53ab4af2015-04-15 19:03:49 +02001095 allwinner,function = "spi0";
1096 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1097 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1098 };
1099
1100 spi1_pins_a: spi1@0 {
Hans de Goede8b1ba942015-06-02 15:53:40 +02001101 allwinner,pins = "PI17", "PI18", "PI19";
1102 allwinner,function = "spi1";
1103 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1104 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1105 };
1106
1107 spi1_cs0_pins_a: spi1_cs0@0 {
1108 allwinner,pins = "PI16";
Hans de Goede53ab4af2015-04-15 19:03:49 +02001109 allwinner,function = "spi1";
1110 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1111 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1112 };
1113
1114 spi2_pins_a: spi2@0 {
Hans de Goede8b1ba942015-06-02 15:53:40 +02001115 allwinner,pins = "PC20", "PC21", "PC22";
Hans de Goede53ab4af2015-04-15 19:03:49 +02001116 allwinner,function = "spi2";
1117 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1118 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1119 };
1120
1121 spi2_pins_b: spi2@1 {
Hans de Goede8b1ba942015-06-02 15:53:40 +02001122 allwinner,pins = "PB15", "PB16", "PB17";
1123 allwinner,function = "spi2";
1124 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1125 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1126 };
1127
1128 spi2_cs0_pins_a: spi2_cs0@0 {
1129 allwinner,pins = "PC19";
1130 allwinner,function = "spi2";
1131 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1132 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1133 };
1134
1135 spi2_cs0_pins_b: spi2_cs0@1 {
1136 allwinner,pins = "PB14";
Hans de Goede53ab4af2015-04-15 19:03:49 +02001137 allwinner,function = "spi2";
1138 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1139 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1140 };
1141
Hans de Goede860fbdd2016-08-18 20:51:12 +02001142 uart0_pins_a: uart0@0 {
1143 allwinner,pins = "PB22", "PB23";
1144 allwinner,function = "uart0";
Hans de Goede53ab4af2015-04-15 19:03:49 +02001145 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1146 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1147 };
1148
Hans de Goede860fbdd2016-08-18 20:51:12 +02001149 uart0_pins_b: uart0@1 {
1150 allwinner,pins = "PF2", "PF4";
1151 allwinner,function = "uart0";
1152 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1153 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1154 };
1155
1156 uart1_pins_a: uart1@0 {
1157 allwinner,pins = "PA10", "PA11";
1158 allwinner,function = "uart1";
Hans de Goede53ab4af2015-04-15 19:03:49 +02001159 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1160 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1161 };
1162 };
1163
1164 timer@01c20c00 {
1165 compatible = "allwinner,sun4i-a10-timer";
1166 reg = <0x01c20c00 0x90>;
1167 interrupts = <22>;
1168 clocks = <&osc24M>;
1169 };
1170
1171 wdt: watchdog@01c20c90 {
1172 compatible = "allwinner,sun4i-a10-wdt";
1173 reg = <0x01c20c90 0x10>;
1174 };
1175
1176 rtc: rtc@01c20d00 {
1177 compatible = "allwinner,sun4i-a10-rtc";
1178 reg = <0x01c20d00 0x20>;
1179 interrupts = <24>;
1180 };
1181
1182 pwm: pwm@01c20e00 {
1183 compatible = "allwinner,sun4i-a10-pwm";
1184 reg = <0x01c20e00 0xc>;
1185 clocks = <&osc24M>;
1186 #pwm-cells = <3>;
1187 status = "disabled";
1188 };
1189
Hans de Goede860fbdd2016-08-18 20:51:12 +02001190 spdif: spdif@01c21000 {
1191 #sound-dai-cells = <0>;
1192 compatible = "allwinner,sun4i-a10-spdif";
1193 reg = <0x01c21000 0x400>;
1194 interrupts = <13>;
1195 clocks = <&apb0_gates 1>, <&spdif_clk>;
1196 clock-names = "apb", "spdif";
1197 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1198 <&dma SUN4I_DMA_NORMAL 2>;
1199 dma-names = "rx", "tx";
1200 status = "disabled";
1201 };
1202
Hans de Goede53ab4af2015-04-15 19:03:49 +02001203 ir0: ir@01c21800 {
1204 compatible = "allwinner,sun4i-a10-ir";
1205 clocks = <&apb0_gates 6>, <&ir0_clk>;
1206 clock-names = "apb", "ir";
1207 interrupts = <5>;
1208 reg = <0x01c21800 0x40>;
1209 status = "disabled";
1210 };
1211
1212 ir1: ir@01c21c00 {
1213 compatible = "allwinner,sun4i-a10-ir";
1214 clocks = <&apb0_gates 7>, <&ir1_clk>;
1215 clock-names = "apb", "ir";
1216 interrupts = <6>;
1217 reg = <0x01c21c00 0x40>;
1218 status = "disabled";
1219 };
1220
1221 lradc: lradc@01c22800 {
1222 compatible = "allwinner,sun4i-a10-lradc-keys";
1223 reg = <0x01c22800 0x100>;
1224 interrupts = <31>;
1225 status = "disabled";
1226 };
1227
Hans de Goede80e5f832016-03-14 17:37:09 +01001228 codec: codec@01c22c00 {
1229 #sound-dai-cells = <0>;
1230 compatible = "allwinner,sun4i-a10-codec";
1231 reg = <0x01c22c00 0x40>;
1232 interrupts = <30>;
1233 clocks = <&apb0_gates 0>, <&codec_clk>;
1234 clock-names = "apb", "codec";
1235 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1236 <&dma SUN4I_DMA_NORMAL 19>;
1237 dma-names = "rx", "tx";
1238 status = "disabled";
1239 };
1240
Hans de Goede53ab4af2015-04-15 19:03:49 +02001241 sid: eeprom@01c23800 {
1242 compatible = "allwinner,sun4i-a10-sid";
1243 reg = <0x01c23800 0x10>;
1244 };
1245
1246 rtp: rtp@01c25000 {
1247 compatible = "allwinner,sun4i-a10-ts";
1248 reg = <0x01c25000 0x100>;
1249 interrupts = <29>;
1250 #thermal-sensor-cells = <0>;
1251 };
1252
1253 uart0: serial@01c28000 {
1254 compatible = "snps,dw-apb-uart";
1255 reg = <0x01c28000 0x400>;
1256 interrupts = <1>;
1257 reg-shift = <2>;
1258 reg-io-width = <4>;
1259 clocks = <&apb1_gates 16>;
1260 status = "disabled";
1261 };
1262
1263 uart1: serial@01c28400 {
1264 compatible = "snps,dw-apb-uart";
1265 reg = <0x01c28400 0x400>;
1266 interrupts = <2>;
1267 reg-shift = <2>;
1268 reg-io-width = <4>;
1269 clocks = <&apb1_gates 17>;
1270 status = "disabled";
1271 };
1272
1273 uart2: serial@01c28800 {
1274 compatible = "snps,dw-apb-uart";
1275 reg = <0x01c28800 0x400>;
1276 interrupts = <3>;
1277 reg-shift = <2>;
1278 reg-io-width = <4>;
1279 clocks = <&apb1_gates 18>;
1280 status = "disabled";
1281 };
1282
1283 uart3: serial@01c28c00 {
1284 compatible = "snps,dw-apb-uart";
1285 reg = <0x01c28c00 0x400>;
1286 interrupts = <4>;
1287 reg-shift = <2>;
1288 reg-io-width = <4>;
1289 clocks = <&apb1_gates 19>;
1290 status = "disabled";
1291 };
1292
1293 uart4: serial@01c29000 {
1294 compatible = "snps,dw-apb-uart";
1295 reg = <0x01c29000 0x400>;
1296 interrupts = <17>;
1297 reg-shift = <2>;
1298 reg-io-width = <4>;
1299 clocks = <&apb1_gates 20>;
1300 status = "disabled";
1301 };
1302
1303 uart5: serial@01c29400 {
1304 compatible = "snps,dw-apb-uart";
1305 reg = <0x01c29400 0x400>;
1306 interrupts = <18>;
1307 reg-shift = <2>;
1308 reg-io-width = <4>;
1309 clocks = <&apb1_gates 21>;
1310 status = "disabled";
1311 };
1312
1313 uart6: serial@01c29800 {
1314 compatible = "snps,dw-apb-uart";
1315 reg = <0x01c29800 0x400>;
1316 interrupts = <19>;
1317 reg-shift = <2>;
1318 reg-io-width = <4>;
1319 clocks = <&apb1_gates 22>;
1320 status = "disabled";
1321 };
1322
1323 uart7: serial@01c29c00 {
1324 compatible = "snps,dw-apb-uart";
1325 reg = <0x01c29c00 0x400>;
1326 interrupts = <20>;
1327 reg-shift = <2>;
1328 reg-io-width = <4>;
1329 clocks = <&apb1_gates 23>;
1330 status = "disabled";
1331 };
1332
1333 i2c0: i2c@01c2ac00 {
1334 compatible = "allwinner,sun4i-a10-i2c";
1335 reg = <0x01c2ac00 0x400>;
1336 interrupts = <7>;
1337 clocks = <&apb1_gates 0>;
1338 status = "disabled";
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1341 };
1342
1343 i2c1: i2c@01c2b000 {
1344 compatible = "allwinner,sun4i-a10-i2c";
1345 reg = <0x01c2b000 0x400>;
1346 interrupts = <8>;
1347 clocks = <&apb1_gates 1>;
1348 status = "disabled";
1349 #address-cells = <1>;
1350 #size-cells = <0>;
1351 };
1352
1353 i2c2: i2c@01c2b400 {
1354 compatible = "allwinner,sun4i-a10-i2c";
1355 reg = <0x01c2b400 0x400>;
1356 interrupts = <9>;
1357 clocks = <&apb1_gates 2>;
1358 status = "disabled";
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1361 };
1362
1363 ps20: ps2@01c2a000 {
1364 compatible = "allwinner,sun4i-a10-ps2";
1365 reg = <0x01c2a000 0x400>;
1366 interrupts = <62>;
1367 clocks = <&apb1_gates 6>;
1368 status = "disabled";
1369 };
1370
1371 ps21: ps2@01c2a400 {
1372 compatible = "allwinner,sun4i-a10-ps2";
1373 reg = <0x01c2a400 0x400>;
1374 interrupts = <63>;
1375 clocks = <&apb1_gates 7>;
1376 status = "disabled";
1377 };
1378 };
1379};