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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the CU824 board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_MPC824X 1
45#define CONFIG_MPC8240 1
46#define CONFIG_CU824 1
47
Wolfgang Denk2ae18242010-10-06 09:05:45 +020048#define CONFIG_SYS_TEXT_BASE 0xFFF00000
wdenkc6097192002-11-03 00:24:07 +000049
50#define CONFIG_CONS_INDEX 1
51#define CONFIG_BAUDRATE 9600
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkc6097192002-11-03 00:24:07 +000053
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010054#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkc6097192002-11-03 00:24:07 +000055
56#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
57#define CONFIG_BOOTDELAY 5
58
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050059/*
60 * BOOTP options
61 */
62#define CONFIG_BOOTP_SUBNETMASK
63#define CONFIG_BOOTP_GATEWAY
64#define CONFIG_BOOTP_HOSTNAME
65#define CONFIG_BOOTP_BOOTPATH
66#define CONFIG_BOOTP_BOOTFILESIZE
67
wdenkc6097192002-11-03 00:24:07 +000068
wdenk414eec32005-04-02 22:37:54 +000069#define CONFIG_TIMESTAMP /* Print image info with timestamp */
70
wdenkc6097192002-11-03 00:24:07 +000071
Jon Loeliger49cf7e82007-07-05 19:52:35 -050072/*
73 * Command line configuration.
wdenkc6097192002-11-03 00:24:07 +000074 */
Jon Loeliger49cf7e82007-07-05 19:52:35 -050075#include <config_cmd_default.h>
76
Wolfgang Denk5728be32007-08-06 01:01:49 +020077#define CONFIG_CMD_BEDBUG
Jon Loeliger49cf7e82007-07-05 19:52:35 -050078#define CONFIG_CMD_DHCP
79#define CONFIG_CMD_PCI
80#define CONFIG_CMD_NFS
81#define CONFIG_CMD_SNTP
wdenkc6097192002-11-03 00:24:07 +000082
83
84/*
85 * Miscellaneous configurable options
86 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_LONGHELP /* undef to save memory */
88#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
89#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000090
91#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
wdenkc6097192002-11-03 00:24:07 +000093#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#ifdef CONFIG_SYS_HUSH_PARSER
95#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkc6097192002-11-03 00:24:07 +000096#endif
97
98/* Print Buffer Size
99 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenkc6097192002-11-03 00:24:07 +0000101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
103#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
104#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenkc6097192002-11-03 00:24:07 +0000105
106/*-----------------------------------------------------------------------
107 * Start addresses for the final memory configuration
108 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_SDRAM_BASE 0x00000000
112#define CONFIG_SYS_FLASH_BASE 0xFF000000
wdenkc6097192002-11-03 00:24:07 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenkc6097192002-11-03 00:24:07 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
wdenkc6097192002-11-03 00:24:07 +0000117
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200118#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenkc6097192002-11-03 00:24:07 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
121#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
124#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000125
126 /* Maximum amount of RAM.
127 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
wdenkc6097192002-11-03 00:24:07 +0000129
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
132#undef CONFIG_SYS_RAMBOOT
wdenkc6097192002-11-03 00:24:07 +0000133#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_RAMBOOT
wdenkc6097192002-11-03 00:24:07 +0000135#endif
136
137
138/*-----------------------------------------------------------------------
139 * Definitions for initial stack pointer and data area
140 */
141
142 /* Size in bytes reserved for initial data
143 */
wdenkc6097192002-11-03 00:24:07 +0000144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200146#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200147#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000148
149/*
150 * NS16550 Configuration
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_NS16550
153#define CONFIG_SYS_NS16550_SERIAL
wdenkc6097192002-11-03 00:24:07 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_NS16550_REG_SIZE 4
wdenkc6097192002-11-03 00:24:07 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_NS16550_CLK (14745600 / 2)
wdenkc6097192002-11-03 00:24:07 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_NS16550_COM1 0xFE800080
160#define CONFIG_SYS_NS16550_COM2 0xFE8000C0
wdenkc6097192002-11-03 00:24:07 +0000161
162/*
163 * Low Level Configuration Settings
164 * (address mappings, register initial values, etc.)
165 * You should know what you are doing if you make changes here.
166 * For the detail description refer to the MPC8240 user's manual.
167 */
168
169#define CONFIG_SYS_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_HZ 1000
wdenkc6097192002-11-03 00:24:07 +0000171
172 /* Bit-field values for MCCR1.
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_ROMNAL 0
175#define CONFIG_SYS_ROMFAL 7
wdenkc6097192002-11-03 00:24:07 +0000176
177 /* Bit-field values for MCCR2.
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_REFINT 430 /* Refresh interval */
wdenkc6097192002-11-03 00:24:07 +0000180
181 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
182 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_BSTOPRE 192
wdenkc6097192002-11-03 00:24:07 +0000184
185 /* Bit-field values for MCCR3.
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
188#define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */
wdenkc6097192002-11-03 00:24:07 +0000189
190 /* Bit-field values for MCCR4.
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
193#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
194#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
195#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
196#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
197#define CONFIG_SYS_ACTORW 2
198#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
wdenkc6097192002-11-03 00:24:07 +0000199
200/* Memory bank settings.
201 * Only bits 20-29 are actually used from these vales to set the
202 * start/end addresses. The upper two bits will always be 0, and the lower
203 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
204 * address. Refer to the MPC8240 book.
205 */
206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_BANK0_START 0x00000000
208#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
209#define CONFIG_SYS_BANK0_ENABLE 1
210#define CONFIG_SYS_BANK1_START 0x3ff00000
211#define CONFIG_SYS_BANK1_END 0x3fffffff
212#define CONFIG_SYS_BANK1_ENABLE 0
213#define CONFIG_SYS_BANK2_START 0x3ff00000
214#define CONFIG_SYS_BANK2_END 0x3fffffff
215#define CONFIG_SYS_BANK2_ENABLE 0
216#define CONFIG_SYS_BANK3_START 0x3ff00000
217#define CONFIG_SYS_BANK3_END 0x3fffffff
218#define CONFIG_SYS_BANK3_ENABLE 0
219#define CONFIG_SYS_BANK4_START 0x3ff00000
220#define CONFIG_SYS_BANK4_END 0x3fffffff
221#define CONFIG_SYS_BANK4_ENABLE 0
222#define CONFIG_SYS_BANK5_START 0x3ff00000
223#define CONFIG_SYS_BANK5_END 0x3fffffff
224#define CONFIG_SYS_BANK5_ENABLE 0
225#define CONFIG_SYS_BANK6_START 0x3ff00000
226#define CONFIG_SYS_BANK6_END 0x3fffffff
227#define CONFIG_SYS_BANK6_ENABLE 0
228#define CONFIG_SYS_BANK7_START 0x3ff00000
229#define CONFIG_SYS_BANK7_END 0x3fffffff
230#define CONFIG_SYS_BANK7_ENABLE 0
wdenkc6097192002-11-03 00:24:07 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_ODCR 0xff
wdenkc6097192002-11-03 00:24:07 +0000233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
235#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
238#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
241#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
244#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
247#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
248#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
249#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
250#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
251#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
252#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
253#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000254
255/*
256 * For booting Linux, the board info and command line data
257 * have to be in the first 8 MB of memory, since this is
258 * the maximum mapped by the Linux kernel during initialization.
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000261
262/*-----------------------------------------------------------------------
263 * FLASH organization
264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */
266#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
wdenkc6097192002-11-03 00:24:07 +0000267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
269#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000270
271 /* Warining: environment is not EMBEDDED in the U-Boot code.
272 * It's stored in flash separately.
273 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200274#define CONFIG_ENV_IS_IN_FLASH 1
wdenkc6097192002-11-03 00:24:07 +0000275#if 0
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200276#define CONFIG_ENV_ADDR 0xFF008000
277#define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */
wdenkc6097192002-11-03 00:24:07 +0000278#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200279#define CONFIG_ENV_ADDR 0xFFFC0000
280#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
281#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
282#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
wdenkc6097192002-11-03 00:24:07 +0000283#endif
284
285/*-----------------------------------------------------------------------
286 * Cache Configuration
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500289#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000291#endif
292
wdenkc6097192002-11-03 00:24:07 +0000293/*-----------------------------------------------------------------------
294 * PCI stuff
295 *-----------------------------------------------------------------------
296 */
297#define CONFIG_PCI /* include pci support */
298#undef CONFIG_PCI_PNP
299
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200300#define CONFIG_NET_MULTI /* Multi ethernet cards support */
wdenkc6097192002-11-03 00:24:07 +0000301
302#define CONFIG_TULIP
303#define CONFIG_TULIP_USE_IO
304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_ETH_DEV_FN 0x7800
306#define CONFIG_SYS_ETH_IOBASE 0x00104000
wdenkc6097192002-11-03 00:24:07 +0000307
wdenk3bac3512003-03-12 10:41:04 +0000308#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk3bac3512003-03-12 10:41:04 +0000310#define PCI_ENET0_IOADDR 0x00104000
311#define PCI_ENET0_MEMADDR 0x80000000
wdenkc6097192002-11-03 00:24:07 +0000312#endif /* __CONFIG_H */