| Nikita Kiryanov | baaa7dd | 2015-02-03 13:32:20 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * pxa_lcd.h - PXA LCD Controller structures |
| 3 | * |
| 4 | * (C) Copyright 2001 |
| 5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #ifndef _PXA_LCD_H_ |
| 11 | #define _PXA_LCD_H_ |
| 12 | |
| 13 | /* |
| 14 | * PXA LCD DMA descriptor |
| 15 | */ |
| 16 | struct pxafb_dma_descriptor { |
| 17 | u_long fdadr; /* Frame descriptor address register */ |
| 18 | u_long fsadr; /* Frame source address register */ |
| 19 | u_long fidr; /* Frame ID register */ |
| 20 | u_long ldcmd; /* Command register */ |
| 21 | }; |
| 22 | |
| 23 | /* |
| 24 | * PXA LCD info |
| 25 | */ |
| 26 | struct pxafb_info { |
| 27 | /* Misc registers */ |
| 28 | u_long reg_lccr3; |
| 29 | u_long reg_lccr2; |
| 30 | u_long reg_lccr1; |
| 31 | u_long reg_lccr0; |
| 32 | u_long fdadr0; |
| 33 | u_long fdadr1; |
| 34 | |
| 35 | /* DMA descriptors */ |
| 36 | struct pxafb_dma_descriptor *dmadesc_fblow; |
| 37 | struct pxafb_dma_descriptor *dmadesc_fbhigh; |
| 38 | struct pxafb_dma_descriptor *dmadesc_palette; |
| 39 | |
| 40 | u_long screen; /* physical address of frame buffer */ |
| 41 | u_long palette; /* physical address of palette memory */ |
| 42 | u_int palette_size; |
| 43 | }; |
| 44 | |
| 45 | /* |
| 46 | * LCD controller stucture for PXA CPU |
| 47 | */ |
| 48 | typedef struct vidinfo { |
| 49 | ushort vl_col; /* Number of columns (i.e. 640) */ |
| 50 | ushort vl_row; /* Number of rows (i.e. 480) */ |
| 51 | ushort vl_width; /* Width of display area in millimeters */ |
| 52 | ushort vl_height; /* Height of display area in millimeters */ |
| 53 | |
| 54 | /* LCD configuration register */ |
| 55 | u_char vl_clkp; /* Clock polarity */ |
| 56 | u_char vl_oep; /* Output Enable polarity */ |
| 57 | u_char vl_hsp; /* Horizontal Sync polarity */ |
| 58 | u_char vl_vsp; /* Vertical Sync polarity */ |
| 59 | u_char vl_dp; /* Data polarity */ |
| 60 | u_char vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ |
| 61 | u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ |
| 62 | u_char vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */ |
| 63 | u_char vl_clor; /* Color, 0 = mono, 1 = color */ |
| 64 | u_char vl_tft; /* 0 = passive, 1 = TFT */ |
| 65 | |
| 66 | /* Horizontal control register. Timing from data sheet */ |
| 67 | ushort vl_hpw; /* Horz sync pulse width */ |
| 68 | u_char vl_blw; /* Wait before of line */ |
| 69 | u_char vl_elw; /* Wait end of line */ |
| 70 | |
| 71 | /* Vertical control register. */ |
| 72 | u_char vl_vpw; /* Vertical sync pulse width */ |
| 73 | u_char vl_bfw; /* Wait before of frame */ |
| 74 | u_char vl_efw; /* Wait end of frame */ |
| 75 | |
| 76 | /* PXA LCD controller params */ |
| 77 | struct pxafb_info pxa; |
| 78 | } vidinfo_t; |
| 79 | |
| 80 | #endif |