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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00002/*
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00004 */
5
Paul Burton7a9d1092013-11-09 10:22:08 +00006#ifndef _MALTA_CONFIG_H
7#define _MALTA_CONFIG_H
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00008
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00009/*
10 * System configuration
11 */
Paul Burton7a9d1092013-11-09 10:22:08 +000012#define CONFIG_MALTA
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000013
Gabor Juhosab413052013-10-24 14:32:00 +020014#define CONFIG_MEMSIZE_IN_BYTES
15
Gabor Juhosfeaa6062013-05-22 03:57:42 +000016#define CONFIG_PCI_GT64120
Paul Burtonbaf37f02013-11-08 11:18:50 +000017#define CONFIG_PCI_MSC01
Gabor Juhosf1957492013-05-22 03:57:44 +000018#define CONFIG_PCNET
Paul Burtone0878af2013-11-08 11:18:52 +000019#define CONFIG_PCNET_79C973
20#define PCNET_HAS_PROM
Gabor Juhosfeaa6062013-05-22 03:57:42 +000021
Paul Burton3ced12a2013-11-08 11:18:55 +000022#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
23
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000024/*
25 * CPU Configuration
26 */
27#define CONFIG_SYS_MHZ 250 /* arbitrary value */
28#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000029
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000030/*
31 * Memory map
32 */
Gabor Juhos10473d02013-11-12 16:47:32 +010033#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000034
Paul Burton0f832b92016-05-26 14:49:36 +010035#ifdef CONFIG_64BIT
36# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
37#else
38# define CONFIG_SYS_SDRAM_BASE 0x80000000
39#endif
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000040#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
41
42#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
43
Paul Burton0f832b92016-05-26 14:49:36 +010044#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000)
45#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
46#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x00800000)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000047
48#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
49#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
Paul Burton67d47522013-11-26 17:45:28 +000050#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000051
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000052/*
53 * Serial driver
54 */
Paul Burton2e7eb122016-05-17 07:43:27 +010055#define CONFIG_SYS_NS16550_PORT_MAPPED
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000056
57/*
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000058 * Flash configuration
59 */
Paul Burton0f832b92016-05-26 14:49:36 +010060#ifdef CONFIG_64BIT
61# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000
62#else
63# define CONFIG_SYS_FLASH_BASE 0xbe000000
64#endif
Gabor Juhos52caee02013-05-22 03:57:39 +000065#define CONFIG_SYS_MAX_FLASH_BANKS 1
66#define CONFIG_SYS_MAX_FLASH_SECT 128
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000067
68/*
Paul Burtonfba6f452013-11-08 11:18:56 +000069 * Environment
70 */
Paul Burtonfba6f452013-11-08 11:18:56 +000071
72/*
Paul Burtonba21a452015-01-29 10:38:20 +000073 * IDE/ATA
74 */
75#define CONFIG_SYS_IDE_MAXBUS 1
76#define CONFIG_SYS_IDE_MAXDEVICE 2
77#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
78#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
79#define CONFIG_SYS_ATA_DATA_OFFSET 0
80#define CONFIG_SYS_ATA_REG_OFFSET 0
81
82/*
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000083 * Commands
84 */
Gabor Juhosfeaa6062013-05-22 03:57:42 +000085
Paul Burton7a9d1092013-11-09 10:22:08 +000086#endif /* _MALTA_CONFIG_H */