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Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Patrick Bruenn98d62e62016-11-04 11:57:02 +01002/*
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +02003 * Copyright 2017 Beckhoff Automation GmbH & Co. KG
4 * based on imx53-qsb.dts
Patrick Bruenn98d62e62016-11-04 11:57:02 +01005 */
6
7/dts-v1/;
8#include "imx53.dtsi"
9
Patrick Bruenn98d62e62016-11-04 11:57:02 +010010/ {
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +020011 model = "Beckhoff CX9020 Embedded PC";
12 compatible = "bhf,cx9020", "fsl,imx53";
Patrick Bruenn98d62e62016-11-04 11:57:02 +010013
14 chosen {
15 stdout-path = &uart2;
16 };
Patrick Bruenn98d62e62016-11-04 11:57:02 +010017
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +020018 memory@70000000 {
19 device_type = "memory";
20 reg = <0x70000000 0x20000000>,
21 <0xb0000000 0x20000000>;
22 };
Patrick Bruenn98d62e62016-11-04 11:57:02 +010023
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +020024 display-0 {
25 #address-cells =<1>;
26 #size-cells = <0>;
27 compatible = "fsl,imx-parallel-display";
28 interface-pix-fmt = "rgb24";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_ipu_disp0>;
Patrick Bruenn98d62e62016-11-04 11:57:02 +010031
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +020032 port@0 {
33 reg = <0>;
Patrick Bruenn98d62e62016-11-04 11:57:02 +010034
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +020035 display0_in: endpoint {
36 remote-endpoint = <&ipu_di0_disp0>;
37 };
Patrick Bruenn98d62e62016-11-04 11:57:02 +010038 };
39
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +020040 port@1 {
41 reg = <1>;
Steffen Dirkwinkel9c2b1b02019-10-23 07:40:40 +020042
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +020043 display0_out: endpoint {
44 remote-endpoint = <&tfp410_in>;
45 };
Patrick Bruenn98d62e62016-11-04 11:57:02 +010046 };
47 };
Patrick Bruenn98d62e62016-11-04 11:57:02 +010048
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +020049 dvi-connector {
50 compatible = "dvi-connector";
51 ddc-i2c-bus = <&i2c2>;
52 digital;
53
54 port {
55 dvi_connector_in: endpoint {
56 remote-endpoint = <&tfp410_out>;
57 };
58 };
59 };
60
61 dvi-converter {
62 compatible = "ti,tfp410";
63
64 ports {
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 port@0 {
69 reg = <0>;
70
71 tfp410_in: endpoint {
72 remote-endpoint = <&display0_out>;
73 };
74 };
75
76 port@1 {
77 reg = <1>;
78
79 tfp410_out: endpoint {
80 remote-endpoint = <&dvi_connector_in>;
81 };
82 };
83 };
84 };
85
86 leds {
87 compatible = "gpio-leds";
88
89 pwr-r {
90 gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
91 default-state = "off";
92 };
93
94 pwr-g {
95 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
96 default-state = "on";
97 };
98
99 pwr-b {
100 gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
101 default-state = "off";
102 };
103
104 sd1-b {
105 linux,default-trigger = "mmc0";
106 gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
107 };
108
109 sd2-b {
110 linux,default-trigger = "mmc1";
111 gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
112 };
113 };
114
115 regulator-3p2v {
116 compatible = "regulator-fixed";
117 regulator-name = "3P2V";
118 regulator-min-microvolt = <3200000>;
119 regulator-max-microvolt = <3200000>;
120 regulator-always-on;
121 };
122
123 reg_usb_vbus: regulator-vbus {
124 compatible = "regulator-fixed";
125 regulator-name = "usb_vbus";
126 regulator-min-microvolt = <5000000>;
127 regulator-max-microvolt = <5000000>;
128 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
129 enable-active-high;
130 };
Patrick Bruenn98d62e62016-11-04 11:57:02 +0100131};
132
Patrick Bruenn7e04b4c2019-01-03 07:54:34 +0100133&esdhc1 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_esdhc1>;
136 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
137 bus-width = <4>;
138 status = "okay";
139};
140
141&esdhc2 {
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_esdhc2>;
144 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
145 bus-width = <4>;
146 status = "okay";
147};
148
Patrick Bruenn98d62e62016-11-04 11:57:02 +0100149&fec {
150 pinctrl-names = "default";
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +0200151 pinctrl-0 = <&pinctrl_fec>;
Patrick Bruenn98d62e62016-11-04 11:57:02 +0100152 phy-mode = "rmii";
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +0200153 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
Patrick Bruenn98d62e62016-11-04 11:57:02 +0100154 status = "okay";
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +0200155};
156
157&i2c2 {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_i2c2>;
160 status = "okay";
161};
162
163&ipu_di0_disp0 {
164 remote-endpoint = <&display0_in>;
165};
166
167&uart2 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart2>;
170 fsl,dte-mode;
171 status = "okay";
Patrick Bruenn98d62e62016-11-04 11:57:02 +0100172};
Steffen Dirkwinkelba1444e2019-10-23 07:40:41 +0200173
174&usbh1 {
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +0200175 vbus-supply = <&reg_usb_vbus>;
Steffen Dirkwinkelba1444e2019-10-23 07:40:41 +0200176 phy_type = "utmi";
177 status = "okay";
178};
179
180&usbotg {
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +0200181 dr_mode = "peripheral";
Steffen Dirkwinkelba1444e2019-10-23 07:40:41 +0200182 status = "okay";
183};
Marcel Ziswiler10f4f3f2022-10-22 23:59:40 +0200184
185&vpu {
186 status = "okay";
187};
188
189&iomuxc {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_hog>;
192
193 pinctrl_hog: hoggrp {
194 fsl,pins = <
195 MX53_PAD_GPIO_0__CCM_CLKO 0x1c4
196 MX53_PAD_GPIO_16__I2C3_SDA 0x1c4
197 MX53_PAD_EIM_D22__GPIO3_22 0x1c4
198 MX53_PAD_EIM_D23__GPIO3_23 0x1e4
199 MX53_PAD_EIM_D24__GPIO3_24 0x1e4
200 >;
201 };
202
203 pinctrl_esdhc1: esdhc1grp {
204 fsl,pins = <
205 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
206 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
207 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
208 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
209 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
210 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
211 MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4
212 MX53_PAD_EIM_D17__GPIO3_17 0x1e4
213 MX53_PAD_GPIO_3__GPIO1_3 0x1c4
214 >;
215 };
216
217 pinctrl_esdhc2: esdhc2grp {
218 fsl,pins = <
219 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
220 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
221 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
222 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
223 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
224 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
225 MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4
226 MX53_PAD_EIM_D20__GPIO3_20 0x1e4
227 MX53_PAD_GPIO_8__GPIO1_8 0x1c4
228 >;
229 };
230
231 pinctrl_fec: fecgrp {
232 fsl,pins = <
233 MX53_PAD_FEC_MDC__FEC_MDC 0x4
234 MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
235 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
236 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
237 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
238 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
239 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
240 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
241 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
242 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
243 >;
244 };
245
246 pinctrl_i2c2: i2c2grp {
247 fsl,pins = <
248 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
249 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
250 >;
251 };
252
253 pinctrl_ipu_disp0: ipudisp0grp {
254 fsl,pins = <
255 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
256 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
257 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
258 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
259 MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
260 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
261 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
262 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
263 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
264 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
265 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
266 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
267 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
268 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
269 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
270 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
271 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
272 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
273 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
274 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
275 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
276 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
277 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
278 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
279 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
280 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
281 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
282 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
283 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
284 >;
285 };
286
287 pinctrl_uart2: uart2grp {
288 fsl,pins = <
289 MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
290 MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4
291 MX53_PAD_EIM_D28__UART2_RTS 0x1e4
292 MX53_PAD_EIM_D29__UART2_CTS 0x1e4
293 >;
294 };
295};