blob: 2d7fe592c8f9404fca2f31a98c231769f9792725 [file] [log] [blame]
Michal Simek64eb13b2019-04-12 12:19:22 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
5 * (C) Copyright 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "Versal System Controller on a2197 Memory Char board RevA";
Michal Simek50d92832019-06-28 13:16:10 +020017 compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA",
Michal Simek64eb13b2019-04-12 12:19:22 +020018 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
19
20 aliases {
21 ethernet0 = &gem0;
Michal Simek64eb13b2019-04-12 12:19:22 +020022 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 mmc0 = &sdhci0;
25 mmc1 = &sdhci1;
Michal Simek531abcb2021-06-03 11:46:50 +020026 nvmem0 = &eeprom;
Michal Simek64eb13b2019-04-12 12:19:22 +020027 rtc0 = &rtc;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &dcc;
31 usb0 = &usb0;
32 usb1 = &usb1;
33 spi0 = &qspi;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
Michal Simek64eb13b2019-04-12 12:19:22 +020039 };
40
41 memory@0 {
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
44 };
Michal Simekeaf96b12019-08-26 11:09:54 +020045
46 ina226-vcc-aux {
47 compatible = "iio-hwmon";
48 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
49 };
50 ina226-vcc-ram {
51 compatible = "iio-hwmon";
52 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
53 };
54 ina226-vcc1v1-lp4 {
55 compatible = "iio-hwmon";
56 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
57 };
58 ina226-vcc1v2-lp4 {
59 compatible = "iio-hwmon";
60 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
61 };
62 ina226-vdd1-1v8-lp4 {
63 compatible = "iio-hwmon";
64 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
65 };
66 ina226-vcc0v6-lp4 {
67 compatible = "iio-hwmon";
68 io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;
69 };
Michal Simek64eb13b2019-04-12 12:19:22 +020070};
71
72&qspi {
73 status = "okay";
74 is-dual = <1>;
75 flash@0 {
Michal Simekb954e882019-08-07 09:58:29 +020076 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Michal Simek64eb13b2019-04-12 12:19:22 +020077 #address-cells = <1>;
78 #size-cells = <1>;
79 reg = <0x0>;
Amit Kumar Mahapatra6e38e2e2022-05-10 16:33:01 +020080 spi-tx-bus-width = <4>;
Michal Simek64eb13b2019-04-12 12:19:22 +020081 spi-rx-bus-width = <4>;
82 spi-max-frequency = <108000000>;
83 };
84};
85
86&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
87 status = "okay";
88 non-removable;
89 disable-wp;
90 bus-width = <8>;
Michal Simek01a6da12020-07-22 17:42:43 +020091 xlnx,mio-bank = <0>; /* FIXME tap delay */
Michal Simek64eb13b2019-04-12 12:19:22 +020092};
93
94&uart0 { /* uart0 MIO38-39 */
95 status = "okay";
Michal Simek64eb13b2019-04-12 12:19:22 +020096};
97
98&uart1 { /* uart1 MIO40-41 */
99 status = "okay";
Michal Simek64eb13b2019-04-12 12:19:22 +0200100};
101
102&sdhci1 { /* sd1 MIO45-51 cd in place */
103 status = "disable";
104 no-1-8-v;
105 disable-wp;
Michal Simek01a6da12020-07-22 17:42:43 +0200106 xlnx,mio-bank = <1>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200107};
108
109&gem0 {
110 status = "okay";
111 phy-handle = <&phy0>;
112 phy-mode = "sgmii"; /* DTG generates this properly 1512 */
113 phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
Michal Simek2975a422019-08-08 12:44:22 +0200114 phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
Michal Simek64eb13b2019-04-12 12:19:22 +0200115 reg = <0>;
116/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
117 };
Michal Simek64eb13b2019-04-12 12:19:22 +0200118};
119
120&gpio {
121 status = "okay";
122 gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
123 "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
124 "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
125 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
126 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
127 "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
128 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
129 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
130 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
131 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
132 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
133 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
134 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
135 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
136 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
137 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
138 "", "", "", "", "", /* 78 - 79 */
139 "", "", "", "", "", /* 80 - 84 */
140 "", "", "", "", "", /* 85 -89 */
141 "", "", "", "", "", /* 90 - 94 */
142 "", "", "", "", "", /* 95 - 99 */
143 "", "", "", "", "", /* 100 - 104 */
144 "", "", "", "", "", /* 105 - 109 */
145 "", "", "", "", "", /* 110 - 114 */
146 "", "", "", "", "", /* 115 - 119 */
147 "", "", "", "", "", /* 120 - 124 */
148 "", "", "", "", "", /* 125 - 129 */
149 "", "", "", "", "", /* 130 - 134 */
150 "", "", "", "", "", /* 135 - 139 */
151 "", "", "", "", "", /* 140 - 144 */
152 "", "", "", "", "", /* 145 - 149 */
153 "", "", "", "", "", /* 150 - 154 */
154 "", "", "", "", "", /* 155 - 159 */
155 "", "", "", "", "", /* 160 - 164 */
156 "", "", "", "", "", /* 165 - 169 */
157 "", "", "", ""; /* 170 - 174 */
158};
159
160&i2c0 { /* MIO 34-35 - can't stay here */
161 status = "okay";
162 clock-frequency = <400000>;
163 i2c-mux@74 { /* u46 */
164 compatible = "nxp,pca9548";
165 #address-cells = <1>;
166 #size-cells = <0>;
167 reg = <0x74>;
168 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
169 i2c@0 { /* PMBUS must be enabled via SW21 */
170 #address-cells = <1>;
171 #size-cells = <0>;
172 reg = <0>;
173 reg_vcc1v2_lp4: tps544@15 { /* u97 */
174 compatible = "ti,tps544b25";
175 reg = <0x15>;
176 };
177 reg_vcc1v1_lp4: tps544@16 { /* u95 */
178 compatible = "ti,tps544b25";
179 reg = <0x16>;
180 };
181 reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
182 compatible = "ti,tps544b25";
183 reg = <0x17>;
184 };
185 /* UTIL_PMBUS connection */
186 reg_vcc1v8: tps544@13 { /* u92 */
187 compatible = "ti,tps544b25";
188 reg = <0x13>;
189 };
190 reg_vcc3v3: tps544@14 { /* u93 */
191 compatible = "ti,tps544b25";
192 reg = <0x14>;
193 };
194 reg_vcc5v0: tps544@1e { /* u94 */
195 compatible = "ti,tps544b25";
196 reg = <0x1e>;
197 };
198 };
199 i2c@1 { /* PMBUS_INA226 */
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <1>;
203 vcc_aux: ina226@42 { /* u86 */
204 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200205 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200206 label = "ina226-vcc-aux";
Michal Simek64eb13b2019-04-12 12:19:22 +0200207 reg = <0x42>;
208 shunt-resistor = <5000>;
209 };
210 vcc_ram: ina226@43 { /* u81 */
211 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200212 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200213 label = "ina226-vcc-ram";
Michal Simek64eb13b2019-04-12 12:19:22 +0200214 reg = <0x43>;
215 shunt-resistor = <5000>;
216 };
217 vcc1v1_lp4: ina226@46 { /* u96 */
218 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200219 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200220 label = "ina226-vcc1v1-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200221 reg = <0x46>;
222 shunt-resistor = <5000>;
223 };
224 vcc1v2_lp4: ina226@47 { /* u98 */
225 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200226 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200227 label = "ina226-vcc1v2-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200228 reg = <0x47>;
229 shunt-resistor = <5000>;
230 };
231 vdd1_1v8_lp4: ina226@48 { /* u100 */
232 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200233 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200234 label = "ina226-vdd1-1v8-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200235 reg = <0x48>;
236 shunt-resistor = <5000>;
237 };
238 vcc0v6_lp4: ina226@49 { /* u101 */
239 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200240 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200241 label = "ina226-vcc0v6-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200242 reg = <0x49>;
243 shunt-resistor = <5000>;
244 };
245 };
246 i2c@2 { /* PMBUS1 */
247 #address-cells = <1>;
248 #size-cells = <0>;
249 reg = <2>;
Michal Simek5f5979f2022-06-15 11:56:55 +0200250 reg_vccint: tps53681@60 { /* u69 - 0xc0 */
Nishant Mittalebb28f22019-07-24 14:58:52 +0530251 compatible = "ti,tps53681", "ti,tps53679";
Michal Simek5f5979f2022-06-15 11:56:55 +0200252 reg = <0x60>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200253 };
254 reg_vcc_pmc: tps544@7 { /* u80 */
255 compatible = "ti,tps544b25";
256 reg = <0x7>;
257 };
258 reg_vcc_ram: tps544@8 { /* u82 */
259 compatible = "ti,tps544b25";
260 reg = <0x8>;
261 };
262 reg_vcc_pslp: tps544@9 { /* u83 */
263 compatible = "ti,tps544b25";
264 reg = <0x9>;
265 };
266 reg_vcc_psfp: tps544@a { /* u84 */
267 compatible = "ti,tps544b25";
268 reg = <0xa>;
269 };
270 reg_vccaux: tps544@d { /* u85 */
271 compatible = "ti,tps544b25";
272 reg = <0xd>;
273 };
274 reg_vccaux_pmc: tps544@e { /* u87 */
275 compatible = "ti,tps544b25";
276 reg = <0xe>;
277 };
278 reg_vcco_500: tps544@f { /* u88 */
279 compatible = "ti,tps544b25";
280 reg = <0xf>;
281 };
282 reg_vcco_501: tps544@10 { /* u89 */
283 compatible = "ti,tps544b25";
284 reg = <0x10>;
285 };
286 reg_vcco_502: tps544@11 { /* u90 */
287 compatible = "ti,tps544b25";
288 reg = <0x11>;
289 };
290 reg_vcco_503: tps544@12 { /* u91 */
291 compatible = "ti,tps544b25";
292 reg = <0x12>;
293 };
294 };
295 i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
296 #address-cells = <1>;
297 #size-cells = <0>;
298 /* reg = <3>; */
299 };
300 i2c@4 { /* LP_I2C_SM */
301 #address-cells = <1>;
302 #size-cells = <0>;
303 reg = <4>;
304 /* connected to U20G */
305 };
306 /* 5-7 unused */
307 };
308};
309
310/* TODO sysctrl via J239 */
311/* TODO samtec J212G/H via J242 */
312/* TODO teensy via U30 PCA9543A bus 1 */
313&i2c1 { /* i2c1 MIO 36-37 */
314 status = "okay";
315 clock-frequency = <400000>;
316
317 /* Must be enabled via J242 */
318 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
319 compatible = "atmel,24c02";
320 reg = <0x51>;
321 };
322
Michal Simek2703d4b2019-06-28 13:52:09 +0200323 i2c-mux@74 { /* u47 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200324 compatible = "nxp,pca9548";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 reg = <0x74>;
328 /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
329 dc_i2c: i2c@0 { /* DC_I2C */
330 #address-cells = <1>;
331 #size-cells = <0>;
332 reg = <0>;
333 /* Use for storing information about SC board */
334 eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
335 compatible = "atmel,24c08";
336 reg = <0x54>;
337 };
338 si570_ref_clk: clock-generator@5d { /* u26 */
339 #clock-cells = <0>;
340 compatible = "silabs,si570";
341 reg = <0x5d>; /* FIXME addr */
342 temperature-stability = <50>;
Michal Simeka34a12f2021-03-09 12:43:42 +0100343 factory-fout = <33333333>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200344 clock-frequency = <33333333>;
345 clock-output-names = "REF_CLK"; /* FIXME */
Michal Simeka34a12f2021-03-09 12:43:42 +0100346 silabs,skip-recall;
Michal Simek64eb13b2019-04-12 12:19:22 +0200347 };
348 /* Connection via Samtec U20D */
349 /* Use for storing information about X-PRC card */
350 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
351 compatible = "atmel,24c02";
352 reg = <0x52>;
353 };
354
355 /* Use for setting up certain features on X-PRC card */
356 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
357 compatible = "nxp,pca9534";
358 reg = <0x22>;
359 gpio-controller; /* IRQ not connected */
360 #gpio-cells = <2>;
361 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
362 "", "", "", "";
363 gtr_sel0 {
364 gpio-hog;
365 gpios = <0 0>;
366 input; /* FIXME add meaning */
367 line-name = "sw4_1";
368 };
369 gtr_sel1 {
370 gpio-hog;
371 gpios = <1 0>;
372 input; /* FIXME add meaning */
373 line-name = "sw4_2";
374 };
375 gtr_sel2 {
376 gpio-hog;
377 gpios = <2 0>;
378 input; /* FIXME add meaning */
379 line-name = "sw4_3";
380 };
381 gtr_sel3 {
382 gpio-hog;
383 gpios = <3 0>;
384 input; /* FIXME add meaning */
385 line-name = "sw4_4";
386 };
387 };
388 };
Michal Simek64eb13b2019-04-12 12:19:22 +0200389 i2c@2 { /* C0_LP4 */
390 #address-cells = <1>;
391 #size-cells = <0>;
392 reg = <2>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200393 si570_c0_lp4: clock-generator@55 { /* u10 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200394 #clock-cells = <0>;
395 compatible = "silabs,si570";
Michal Simek2703d4b2019-06-28 13:52:09 +0200396 reg = <0x55>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200397 temperature-stability = <50>;
398 factory-fout = <30000000>;
399 clock-frequency = <30000000>;
400 clock-output-names = "C0_LP4_SI570_CLK";
401 };
402 };
403 i2c@3 { /* C1_LP4 */
404 #address-cells = <1>;
405 #size-cells = <0>;
406 reg = <3>;
407 si570_c1_lp4: clock-generator@5d { /* u10 */
408 #clock-cells = <0>;
409 compatible = "silabs,si570";
410 reg = <0x5d>; /* FIXME addr */
411 temperature-stability = <50>;
412 factory-fout = <30000000>;
413 clock-frequency = <30000000>;
414 clock-output-names = "C1_LP4_SI570_CLK";
415 };
416 };
417 i2c@4 { /* C2_LP4 */
418 #address-cells = <1>;
419 #size-cells = <0>;
420 reg = <4>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200421 si570_c2_lp4: clock-generator@55 { /* u10 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200422 #clock-cells = <0>;
423 compatible = "silabs,si570";
Michal Simek2703d4b2019-06-28 13:52:09 +0200424 reg = <0x55>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200425 temperature-stability = <50>;
426 factory-fout = <30000000>;
427 clock-frequency = <30000000>;
428 clock-output-names = "C2_LP4_SI570_CLK";
429 };
430 };
431 i2c@5 { /* C3_LP4 */
432 #address-cells = <1>;
433 #size-cells = <0>;
434 reg = <5>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200435 si570_c3_lp4: clock-generator@55 { /* u15 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200436 #clock-cells = <0>;
437 compatible = "silabs,si570";
Michal Simek2703d4b2019-06-28 13:52:09 +0200438 reg = <0x55>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200439 temperature-stability = <50>;
440 factory-fout = <30000000>;
441 clock-frequency = <30000000>;
442 clock-output-names = "C3_LP4_SI570_CLK";
443 };
444 };
445 i2c@6 { /* HSDP_SI570 */
446 #address-cells = <1>;
447 #size-cells = <0>;
448 reg = <6>;
449 si570_hsdp: clock-generator@5d { /* u19 */
450 #clock-cells = <0>;
451 compatible = "silabs,si570";
452 reg = <0x5d>; /* FIXME addr */
453 temperature-stability = <50>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200454 factory-fout = <156250000>;
455 clock-frequency = <156250000>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200456 clock-output-names = "HSDP_SI570";
457 };
458 };
459 };
460};
461
462&usb0 {
463 status = "okay";
Michal Simek64eb13b2019-04-12 12:19:22 +0200464};
465
466&dwc3_0 {
467 status = "okay";
468 dr_mode = "host";
469 /* dr_mode = "peripheral"; */
470 maximum-speed = "high-speed";
471};
472
473&usb1 {
474 status = "disabled"; /* not at mem board */
Michal Simek64eb13b2019-04-12 12:19:22 +0200475};
476
477&dwc3_1 {
478 /delete-property/ phy-names ;
479 /delete-property/ phys ;
480 maximum-speed = "high-speed";
481 snps,dis_u2_susphy_quirk ;
482 snps,dis_u3_susphy_quirk ;
483 status = "disabled";
484};