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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * board/config_GEN860T.h - board specific configuration options
27 */
28
29#ifndef __CONFIG_GEN860T_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 */
35#define CONFIG_MPC860
36#define CONFIG_GEN860T
37
38/*
39 * Identify the board
40 */
wdenk7aa78612003-05-03 15:50:43 +000041#if !defined(CONFIG_SC)
Wolfgang Denk53677ef2008-05-20 16:00:29 +020042#define CONFIG_IDENT_STRING " B2"
wdenk7aa78612003-05-03 15:50:43 +000043#else
Wolfgang Denk53677ef2008-05-20 16:00:29 +020044#define CONFIG_IDENT_STRING " SC"
wdenk7aa78612003-05-03 15:50:43 +000045#endif
wdenk5b1d7132002-11-03 00:07:02 +000046
47/*
48 * Don't depend on the RTC clock to determine clock frequency -
49 * the 860's internal rtc uses a 32.768 KHz clock which is
50 * generated by the DS1337 - and the DS1337 clock can be turned off.
51 */
wdenk7aa78612003-05-03 15:50:43 +000052#if !defined(CONFIG_SC)
Wolfgang Denk53677ef2008-05-20 16:00:29 +020053#define CONFIG_8xx_GCLK_FREQ 66600000
wdenk7aa78612003-05-03 15:50:43 +000054#else
Wolfgang Denk53677ef2008-05-20 16:00:29 +020055#define CONFIG_8xx_GCLK_FREQ 48000000
wdenk7aa78612003-05-03 15:50:43 +000056#endif
wdenk5b1d7132002-11-03 00:07:02 +000057
58/*
59 * The RS-232 console port is on SMC1
60 */
61#define CONFIG_8xx_CONS_SMC1
Wolfgang Denk53677ef2008-05-20 16:00:29 +020062#define CONFIG_BAUDRATE 38400
wdenk5b1d7132002-11-03 00:07:02 +000063
64/*
65 * Set allowable console baud rates
66 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020067#define CFG_BAUDRATE_TABLE { 9600, \
68 19200, \
69 38400, \
70 57600, \
71 115200, \
72 }
wdenk5b1d7132002-11-03 00:07:02 +000073
74/*
75 * Print console information
76 */
77#undef CFG_CONSOLE_INFO_QUIET
78
79/*
80 * Set the autoboot delay in seconds. A delay of -1 disables autoboot
81 */
82#define CONFIG_BOOTDELAY 5
83
84/*
85 * Pass the clock frequency to the Linux kernel in units of MHz
86 */
87#define CONFIG_CLOCKS_IN_MHZ
88
89#define CONFIG_PREBOOT \
90 "echo;echo"
91
92#undef CONFIG_BOOTARGS
93#define CONFIG_BOOTCOMMAND \
94 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010095 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
96 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk5b1d7132002-11-03 00:07:02 +000097 "bootm"
98
99/*
100 * Turn off echo for serial download by default. Allow baud rate to be changed
101 * for downloads
102 */
103#undef CONFIG_LOADS_ECHO
104#define CFG_LOADS_BAUD_CHANGE
105
106/*
107 * Set default load address for tftp network downloads
108 */
109#define CFG_TFTP_LOADADDR 0x01000000
110
111/*
112 * Turn off the watchdog timer
113 */
114#undef CONFIG_WATCHDOG
115
116/*
117 * Do not reboot if a panic occurs
118 */
119#define CONFIG_PANIC_HANG
120
121/*
122 * Enable the status LED
123 */
124#define CONFIG_STATUS_LED
125
126/*
127 * Reset address. We pick an address such that when an instruction
128 * is executed at that address, a machine check exception occurs
129 */
130#define CFG_RESET_ADDRESS ((ulong) -1)
131
132/*
133 * BOOTP options
134 */
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500135#define CONFIG_BOOTP_SUBNETMASK
136#define CONFIG_BOOTP_GATEWAY
137#define CONFIG_BOOTP_HOSTNAME
138#define CONFIG_BOOTP_BOOTPATH
139#define CONFIG_BOOTP_BOOTFILESIZE
140
wdenk5b1d7132002-11-03 00:07:02 +0000141
142/*
143 * The GEN860T network interface uses the on-chip 10/100 FEC with
144 * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
145 * MII address is hardwired on the board to zero.
146 */
147#define CONFIG_FEC_ENET
148#define CFG_DISCOVER_PHY
149#define CONFIG_MII
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500150#define CONFIG_MII_INIT 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200151#define CONFIG_PHY_ADDR 0
wdenk5b1d7132002-11-03 00:07:02 +0000152
153/*
154 * Set default IP stuff just to get bootstrap entries into the
155 * environment so that we can autoscript the full default environment.
156 */
157#define CONFIG_ETHADDR 9a:52:63:15:85:25
wdenk7aa78612003-05-03 15:50:43 +0000158#define CONFIG_SERVERIP 10.0.4.201
wdenk5b1d7132002-11-03 00:07:02 +0000159#define CONFIG_IPADDR 10.0.4.111
160
161/*
162 * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
163 * the MPC860T I2C interface.
164 */
165#define CFG_I2C_EEPROM_ADDR 0x50
166#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
167#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */
168#define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */
169#define CFG_ENV_EEPROM_SIZE (32 * 1024)
170
wdenk5b1d7132002-11-03 00:07:02 +0000171/*
wdenk7aa78612003-05-03 15:50:43 +0000172 * Enable I2C and select the hardware/software driver
wdenk5b1d7132002-11-03 00:07:02 +0000173 */
wdenk7aa78612003-05-03 15:50:43 +0000174#define CONFIG_HARD_I2C 1 /* CPM based I2C */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200175#undef CONFIG_SOFT_I2C /* Bit-banged I2C */
wdenk7aa78612003-05-03 15:50:43 +0000176
177#ifdef CONFIG_HARD_I2C
178#define CFG_I2C_SPEED 100000 /* clock speed in Hz */
179#define CFG_I2C_SLAVE 0xFE /* I2C slave address */
180#endif
181
182#ifdef CONFIG_SOFT_I2C
wdenk5b1d7132002-11-03 00:07:02 +0000183#define PB_SCL 0x00000020 /* PB 26 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200184#define PB_SDA 0x00000010 /* PB 27 */
wdenk5b1d7132002-11-03 00:07:02 +0000185#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
186#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
187#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
188#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
189#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
190 else immr->im_cpm.cp_pbdat &= ~PB_SDA
191#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
192 else immr->im_cpm.cp_pbdat &= ~PB_SCL
193#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
wdenk7aa78612003-05-03 15:50:43 +0000194#endif
wdenk5b1d7132002-11-03 00:07:02 +0000195
196/*
197 * Allow environment overwrites by anyone
198 */
199#define CONFIG_ENV_OVERWRITE
200
wdenk7aa78612003-05-03 15:50:43 +0000201#if !defined(CONFIG_SC)
wdenk5b1d7132002-11-03 00:07:02 +0000202/*
203 * The MPC860's internal RTC is horribly broken in rev D masks. Three
204 * internal MPC860T circuit nodes were inadvertently left floating; this
205 * causes KAPWR current in power down mode to be three orders of magnitude
206 * higher than specified in the datasheet (from 10 uA to 10 mA). No
207 * reasonable battery can keep that kind RTC running during powerdown for any
208 * length of time, so we use an external RTC on the I2C bus instead.
209 */
wdenk5b1d7132002-11-03 00:07:02 +0000210#define CONFIG_RTC_DS1337
wdenk8bde7f72003-06-27 21:31:46 +0000211#define CFG_I2C_RTC_ADDR 0x68
wdenk7aa78612003-05-03 15:50:43 +0000212
213#else
214/*
215 * No external RTC on SC variant, so we're stuck with the internal one.
216 */
217#define CONFIG_RTC_MPC8xx
218#endif
wdenk5b1d7132002-11-03 00:07:02 +0000219
220/*
wdenk7aa78612003-05-03 15:50:43 +0000221 * Power On Self Test support
wdenk5b1d7132002-11-03 00:07:02 +0000222 */
wdenk7aa78612003-05-03 15:50:43 +0000223#define CONFIG_POST ( CFG_POST_CACHE | \
224 CFG_POST_MEMORY | \
225 CFG_POST_CPU | \
226 CFG_POST_UART | \
227 CFG_POST_SPR )
228
Jon Loeliger60a08762007-07-07 21:04:26 -0500229
wdenk5b1d7132002-11-03 00:07:02 +0000230/*
Jon Loeliger60a08762007-07-07 21:04:26 -0500231 * Command line configuration.
wdenk5b1d7132002-11-03 00:07:02 +0000232 */
Jon Loeliger60a08762007-07-07 21:04:26 -0500233#include <config_cmd_default.h>
234
235#define CONFIG_CMD_ASKENV
236#define CONFIG_CMD_DHCP
237#define CONFIG_CMD_I2C
238#define CONFIG_CMD_EEPROM
239#define CONFIG_CMD_REGINFO
240#define CONFIG_CMD_IMMAP
241#define CONFIG_CMD_ELF
242#define CONFIG_CMD_DATE
243#define CONFIG_CMD_FPGA
244#define CONFIG_CMD_MII
245#define CONFIG_CMD_BEDBUG
wdenk7aa78612003-05-03 15:50:43 +0000246
247#if !defined(CONFIG_SC)
Jon Loeliger60a08762007-07-07 21:04:26 -0500248 #define CONFIG_CMD_DOC
wdenk7aa78612003-05-03 15:50:43 +0000249#endif
wdenk5b1d7132002-11-03 00:07:02 +0000250
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500251#ifdef CONFIG_POST
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200252#define CONFIG_CMD_DIAG
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500253#endif
Jon Loeliger60a08762007-07-07 21:04:26 -0500254
wdenk5b1d7132002-11-03 00:07:02 +0000255/*
256 * There is no IDE/PCMCIA hardware support on the board.
257 */
258#undef CONFIG_IDE_PCMCIA
259#undef CONFIG_IDE_LED
260#undef CONFIG_IDE_RESET
261
262/*
263 * Enable the call to misc_init_r() for miscellaneous platform
264 * dependent initialization.
265 */
266#define CONFIG_MISC_INIT_R
267
268/*
269 * Enable call to last_stage_init() so we can twiddle some LEDS :)
270 */
271#define CONFIG_LAST_STAGE_INIT
272
273/*
274 * Virtex2 FPGA configuration support
275 */
276#define CONFIG_FPGA_COUNT 1
Matthias Fuchs01335022007-12-27 17:12:34 +0100277#define CONFIG_FPGA
278#define CONFIG_FPGA_XILINX
279#define CONFIG_FPGA_VIRTEX2
wdenk5b1d7132002-11-03 00:07:02 +0000280#define CFG_FPGA_PROG_FEEDBACK
281
282
Jean-Christophe PLAGNIOL-VILLARDcc4a0ce2008-08-13 01:40:43 +0200283#define CONFIG_NAND_LEGACY
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100284
wdenk5b1d7132002-11-03 00:07:02 +0000285/*
286 * Verbose help from command monitor.
287 */
288#define CFG_LONGHELP
wdenk7aa78612003-05-03 15:50:43 +0000289#if !defined(CONFIG_SC)
290#define CFG_PROMPT "B2> "
291#else
292#define CFG_PROMPT "SC> "
293#endif
294
wdenk5b1d7132002-11-03 00:07:02 +0000295
296/*
297 * Use the "hush" command parser
298 */
299#define CFG_HUSH_PARSER
300#define CFG_PROMPT_HUSH_PS2 "> "
301
302/*
303 * Set buffer size for console I/O
304 */
Jon Loeliger60a08762007-07-07 21:04:26 -0500305#if defined(CONFIG_CMD_KGDB)
wdenk5b1d7132002-11-03 00:07:02 +0000306#define CFG_CBSIZE 1024
307#else
308#define CFG_CBSIZE 256
309#endif
310
311/*
312 * Print buffer size
313 */
314#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
315
316/*
317 * Maximum number of arguments that a command can accept
318 */
319#define CFG_MAXARGS 16
320
321/*
322 * Boot argument buffer size
323 */
324#define CFG_BARGSIZE CFG_CBSIZE
325
326/*
327 * Default memory test range
328 */
329#define CFG_MEMTEST_START 0x0100000
330#define CFG_MEMTEST_END (CFG_MEMTEST_START + (128 * 1024))
331
332/*
333 * Select the more full-featured memory test
334 */
335#define CFG_ALT_MEMTEST
336
337/*
338 * Default load address
339 */
340#define CFG_LOAD_ADDR 0x01000000
341
342/*
343 * Set decrementer frequency (1 ms ticks)
344 */
345#define CFG_HZ 1000
346
347/*
348 * Device memory map (after SDRAM remap to 0x0):
349 *
350 * CS Device Base Addr Size
351 * ----------------------------------------------------
352 * CS0* Flash 0x40000000 64 M
353 * CS1* SDRAM 0x00000000 16 M
354 * CS2* Disk-On-Chip 0x50000000 32 K
355 * CS3* FPGA 0x60000000 64 M
356 * CS4* SelectMap 0x70000000 32 K
357 * CS5* Mil-Std 1553 I/F 0x80000000 32 K
358 * CS6* Unused
359 * CS7* Unused
360 * IMMR 860T Registers 0xfff00000
361 */
362
363/*
364 * Base addresses and block sizes
365 */
366#define CFG_IMMR 0xFF000000
367
368#define SDRAM_BASE 0x00000000
369#define SDRAM_SIZE (64 * 1024 * 1024)
370
371#define FLASH_BASE 0x40000000
372#define FLASH_SIZE (16 * 1024 * 1024)
373
374#define DOC_BASE 0x50000000
375#define DOC_SIZE (32 * 1024)
376
377#define FPGA_BASE 0x60000000
378#define FPGA_SIZE (64 * 1024 * 1024)
379
380#define SELECTMAP_BASE 0x70000000
381#define SELECTMAP_SIZE (32 * 1024)
382
383#define M1553_BASE 0x80000000
384#define M1553_SIZE (64 * 1024)
385
386/*
387 * Definitions for initial stack pointer and data area (in DPRAM)
388 */
389#define CFG_INIT_RAM_ADDR CFG_IMMR
390#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200391#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
wdenk5b1d7132002-11-03 00:07:02 +0000392#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
393#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
394
395/*
396 * Start addresses for the final memory configuration
397 * (Set up by the startup code)
398 * Please note that CFG_SDRAM_BASE _must_ start at 0
399 */
400#define CFG_SDRAM_BASE SDRAM_BASE
401
402/*
403 * FLASH organization
404 */
405#define CFG_FLASH_BASE FLASH_BASE
406#define CFG_FLASH_SIZE FLASH_SIZE
407#define CFG_FLASH_SECT_SIZE (128 * 1024)
408#define CFG_MAX_FLASH_BANKS 1
409#define CFG_MAX_FLASH_SECT 128
410
411/*
412 * The timeout values are for an entire chip and are in milliseconds.
413 * Yes I know that the write timeout is huge. Accroding to the
414 * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
415 * case VCC and temp after 100K programming cycles. It works out
416 * to 280 minutes (might as well be forever).
417 */
418#define CFG_FLASH_ERASE_TOUT (CFG_MAX_FLASH_SECT * 5000)
419#define CFG_FLASH_WRITE_TOUT (CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
420
421/*
422 * Allow direct writes to FLASH from tftp transfers (** dangerous **)
423 */
424#define CFG_DIRECT_FLASH_TFTP
425
426/*
427 * Reserve memory for U-Boot.
428 */
wdenk7aa78612003-05-03 15:50:43 +0000429#define CFG_MAX_UBOOT_SECTS 4
430#define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
431#define CFG_MONITOR_BASE CFG_FLASH_BASE
wdenk5b1d7132002-11-03 00:07:02 +0000432
433/*
434 * Select environment placement. NOTE that u-boot.lds must
435 * be edited if this is changed!
436 */
437#undef CFG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200438#define CONFIG_ENV_IS_IN_EEPROM
wdenk5b1d7132002-11-03 00:07:02 +0000439
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200440#if defined(CONFIG_ENV_IS_IN_EEPROM)
wdenk5b1d7132002-11-03 00:07:02 +0000441#define CFG_ENV_SIZE (2 * 1024)
442#define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024))
443#else
wdenk7aa78612003-05-03 15:50:43 +0000444#define CFG_ENV_SIZE 0x1000
445#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE
446
447/*
448 * This ultimately gets passed right into the linker script, so we have to
449 * use a number :(
450 */
451#define CFG_ENV_OFFSET 0x060000
wdenk5b1d7132002-11-03 00:07:02 +0000452#endif
453
454/*
455 * Reserve memory for malloc()
456 */
457#define CFG_MALLOC_LEN (128 * 1024)
458
459/*
460 * For booting Linux, the board info and command line data
461 * have to be in the first 8 MB of memory, since this is
462 * the maximum mapped by the Linux kernel during initialization.
463 */
464#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
465
466/*
467 * Cache Configuration
468 */
469#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger60a08762007-07-07 21:04:26 -0500470#if defined(CONFIG_CMD_KGDB)
wdenk5b1d7132002-11-03 00:07:02 +0000471#define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */
472#endif
473
474/*------------------------------------------------------------------------
wdenk7aa78612003-05-03 15:50:43 +0000475 * SYPCR - System Protection Control UM 11-9
wdenk5b1d7132002-11-03 00:07:02 +0000476 * -----------------------------------------------------------------------
477 * SYPCR can only be written once after reset!
478 *
479 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
480 */
481#if defined(CONFIG_WATCHDOG)
482#define CFG_SYPCR ( SYPCR_SWTC | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200483 SYPCR_BMT | \
484 SYPCR_BME | \
485 SYPCR_SWF | \
486 SYPCR_SWE | \
wdenk5b1d7132002-11-03 00:07:02 +0000487 SYPCR_SWRI | \
488 SYPCR_SWP \
489 )
490#else
491#define CFG_SYPCR ( SYPCR_SWTC | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200492 SYPCR_BMT | \
493 SYPCR_BME | \
494 SYPCR_SWF | \
wdenk5b1d7132002-11-03 00:07:02 +0000495 SYPCR_SWP \
496 )
497#endif
498
499/*-----------------------------------------------------------------------
500 * SIUMCR - SIU Module Configuration UM 11-6
501 *-----------------------------------------------------------------------
502 * Set debug pin mux, enable SPKROUT and GPLB5*.
503 */
504#define CFG_SIUMCR ( SIUMCR_DBGC11 | \
505 SIUMCR_DBPC11 | \
506 SIUMCR_MLRC11 | \
507 SIUMCR_GB5E \
508 )
509
510/*-----------------------------------------------------------------------
511 * TBSCR - Time Base Status and Control UM 11-26
512 *-----------------------------------------------------------------------
513 * Clear Reference Interrupt Status, Timebase freeze enabled
514 */
515#define CFG_TBSCR ( TBSCR_REFA | \
516 TBSCR_REFB | \
517 TBSCR_TBF \
518 )
519
520/*-----------------------------------------------------------------------
521 * RTCSC - Real-Time Clock Status and Control Register UM 11-27
522 *-----------------------------------------------------------------------
523 */
524#define CFG_RTCSC ( RTCSC_SEC | \
525 RTCSC_ALR | \
526 RTCSC_RTF | \
527 RTCSC_RTE \
528 )
529
530/*-----------------------------------------------------------------------
531 * PISCR - Periodic Interrupt Status and Control UM 11-31
532 *-----------------------------------------------------------------------
533 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
534 */
535#define CFG_PISCR ( PISCR_PS | \
536 PISCR_PITF \
537 )
538
539/*-----------------------------------------------------------------------
540 * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30
541 *-----------------------------------------------------------------------
542 * Reset PLL lock status sticky bit, timer expired status bit and timer
543 * interrupt status bit. Set MF for 1:2:1 mode.
544 */
545#define CFG_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \
546 PLPRCR_SPLSS | \
547 PLPRCR_TEXPS | \
548 PLPRCR_TMIST \
549 )
550
551/*-----------------------------------------------------------------------
552 * SCCR - System Clock and reset Control Register UM 15-27
553 *-----------------------------------------------------------------------
554 * Set clock output, timebase and RTC source and divider,
555 * power management and some other internal clocks
556 */
557#define SCCR_MASK SCCR_EBDF11
558
wdenk7aa78612003-05-03 15:50:43 +0000559#if !defined(CONFIG_SC)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200560#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
561 SCCR_COM00 | /* full strength CLKOUT */ \
562 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
563 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
wdenk5b1d7132002-11-03 00:07:02 +0000564 SCCR_DFNL000 | \
565 SCCR_DFNH000 \
566 )
wdenk7aa78612003-05-03 15:50:43 +0000567#else
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200568#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
569 SCCR_COM00 | /* full strength CLKOUT */ \
570 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
571 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
wdenk7aa78612003-05-03 15:50:43 +0000572 SCCR_DFNL000 | \
573 SCCR_DFNH000 | \
574 SCCR_RTDIV | \
575 SCCR_RTSEL \
576 )
577#endif
wdenk5b1d7132002-11-03 00:07:02 +0000578
579/*-----------------------------------------------------------------------
580 * DER - Debug Enable Register UM 37-46
581 *-----------------------------------------------------------------------
582 * Mask all events that can cause entry into debug mode
583 */
584#define CFG_DER 0
585
586/*
587 * Initialize Memory Controller:
588 *
589 * BR0 and OR0 (FLASH memory)
590 */
591#define FLASH_BASE0_PRELIM FLASH_BASE
592
593/*
594 * Flash address mask
595 */
596#define CFG_PRELIM_OR_AM 0xfe000000
597
598/*
599 * FLASH timing:
600 * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
601 */
602#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | \
603 OR_ACS_DIV2 | \
604 OR_BI | \
605 OR_SCY_2_CLK | \
606 OR_TRLX | \
607 OR_EHTR \
608 )
609
610#define CFG_OR0_PRELIM ( CFG_PRELIM_OR_AM | \
611 CFG_OR_TIMING_FLASH \
612 )
613
614#define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \
615 BR_MS_GPCM | \
616 BR_PS_8 | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200617 BR_V \
wdenk5b1d7132002-11-03 00:07:02 +0000618 )
619
620/*
621 * SDRAM configuration
622 */
623#define CFG_OR1_AM 0xfc000000
624#define CFG_OR1 ( (CFG_OR1_AM & OR_AM_MSK) | \
625 OR_CSNT_SAM \
626 )
627
628#define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200629 BR_MS_UPMA | \
630 BR_PS_32 | \
631 BR_V \
wdenk5b1d7132002-11-03 00:07:02 +0000632 )
633
634/*
635 * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
636 * of 256 MBit SDRAM
637 */
638#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16
639
640/*
641 * Periodic timer for refresh @ 33 MHz system clock
642 */
643#define CFG_MAMR_PTA 64
644
645/*
646 * MAMR settings for SDRAM
647 */
648#define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200649 MAMR_PTAE | \
wdenk5b1d7132002-11-03 00:07:02 +0000650 MAMR_AMA_TYPE_1 | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200651 MAMR_DSA_1_CYCL | \
wdenk5b1d7132002-11-03 00:07:02 +0000652 MAMR_G0CLA_A10 | \
653 MAMR_RLFA_1X | \
654 MAMR_WLFA_1X | \
655 MAMR_TLFA_4X \
656 )
657
658/*
659 * CS2* configuration for Disk On Chip:
660 * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
661 * no burst.
662 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200663#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000664 OR_CSNT_SAM | \
665 OR_ACS_DIV2 | \
666 OR_BI | \
667 OR_SCY_2_CLK | \
668 OR_TRLX | \
669 OR_EHTR \
670 )
671
672#define CFG_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \
673 BR_PS_8 | \
674 BR_MS_GPCM | \
675 BR_V \
676 )
677
678/*
679 * CS3* configuration for FPGA:
680 * 33 MHz bus with SCY=15, no burst.
681 * The FPGA uses TA and TEA to terminate bus cycles, but we
682 * clear SETA and set the cycle length to a large number so that
683 * the cycle will still complete even if there is a configuration
684 * error that prevents TA from asserting on FPGA accesss.
685 */
686#define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \
687 OR_SCY_15_CLK | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200688 OR_BI \
wdenk5b1d7132002-11-03 00:07:02 +0000689 )
690
691#define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \
692 BR_PS_32 | \
693 BR_MS_GPCM | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200694 BR_V \
wdenk5b1d7132002-11-03 00:07:02 +0000695 )
696/*
697 * CS4* configuration for FPGA SelectMap configuration interface.
698 * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
699 * of GCLK1_50
700 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200701#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000702 OR_G5LS | \
703 OR_BI \
704 )
705
706#define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \
707 BR_PS_8 | \
708 BR_MS_UPMB | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200709 BR_V \
wdenk5b1d7132002-11-03 00:07:02 +0000710 )
711
712/*
713 * CS5* configuration for Mil-Std 1553 databus interface.
714 * 33 MHz bus, GPCM, no burst.
715 * The 1553 interface uses TA and TEA to terminate bus cycles,
716 * but we clear SETA and set the cycle length to a large number so that
717 * the cycle will still complete even if there is a configuration
718 * error that prevents TA from asserting on FPGA accesss.
719 */
720#define CFG_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
721 OR_SCY_15_CLK | \
722 OR_EHTR | \
723 OR_TRLX | \
724 OR_CSNT_SAM | \
725 OR_BI \
726 )
727
728#define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \
729 BR_PS_16 | \
730 BR_MS_GPCM | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200731 BR_V \
wdenk5b1d7132002-11-03 00:07:02 +0000732 )
733
734/*
735 * Boot Flags
736 */
737#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
738#define BOOTFLAG_WARM 0x02 /* Software reboot */
739
740/*
741 * Disk On Chip (millenium) configuration
742 */
wdenk7aa78612003-05-03 15:50:43 +0000743#if !defined(CONFIG_SC)
wdenk5b1d7132002-11-03 00:07:02 +0000744#define CFG_MAX_DOC_DEVICE 1
745#undef CFG_DOC_SUPPORT_2000
746#define CFG_DOC_SUPPORT_MILLENNIUM
747#undef CFG_DOC_PASSIVE_PROBE
wdenk7aa78612003-05-03 15:50:43 +0000748#endif
wdenk5b1d7132002-11-03 00:07:02 +0000749
750/*
751 * FEC interrupt assignment
752 */
753#define FEC_INTERRUPT SIU_LEVEL1
754
755/*
756 * Sanity checks
757 */
758#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
759#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
760#endif
761
762#endif /* __CONFIG_GEN860T_H */