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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / bb3bcfa2426cc6a0aecec7270e3ee67ca843a125 / . / cpu / i386 / interrupts.c
blob: 4b57437193079a7df614d62aaac81e513c131319 [file] [log] [blame]
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]1/*
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]2 * (C) Copyright 2008
3 * Graeme Russ, graeme.russ@gmail.com.
4 *
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]5 * (C) Copyright 2002
6 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
Graeme Russ9933d602008-12-07 10:29:01 +1100[diff] [blame]28#include <asm/interrupt.h>
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]29
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]30#define DECLARE_INTERRUPT(x) \
31 ".globl irq_"#x"\n" \
Graeme Russ0fc1b492009-11-24 20:04:19 +1100[diff] [blame]32 ".hidden irq_"#x"\n" \
33 ".type irq_"#x", @function\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]34 "irq_"#x":\n" \
35 "pushl %ebp\n" \
36 "movl %esp,%ebp\n" \
37 "pusha\n" \
38 "pushl $"#x"\n" \
39 "jmp irq_common_entry\n"
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]40
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]41struct idt_entry {
42 u16 base_low;
43 u16 selector;
44 u8 res;
45 u8 access;
46 u16 base_high;
47} __attribute__ ((packed));
48
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]49struct desc_ptr {
50 unsigned short size;
51 unsigned long address;
52 unsigned short segment;
53} __attribute__((packed));
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]54
55struct idt_entry idt[256];
56
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]57struct desc_ptr idt_ptr;
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]58
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]59static inline void load_idt(const struct desc_ptr *dtr)
60{
61 asm volatile("cs lidt %0"::"m" (*dtr));
62}
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]63
Graeme Russabf0cd32009-02-24 21:13:40 +1100[diff] [blame]64void set_vector(u8 intnum, void *routine)
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]65{
Graeme Russ1c409bc2009-11-24 20:04:21 +1100[diff] [blame]66 idt[intnum].base_high = (u16)((u32)(routine) >> 16);
67 idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]68}
69
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]70void irq_0(void);
71void irq_1(void);
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]72
Graeme Russabf0cd32009-02-24 21:13:40 +1100[diff] [blame]73int cpu_init_interrupts(void)
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]74{
75 int i;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]76
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]77 int irq_entry_size = irq_1 - irq_0;
78 void *irq_entry = (void *)irq_0;
79
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]80 /* Just in case... */
81 disable_interrupts();
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]82
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]83 /* Setup the IDT */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]84 for (i=0;i<256;i++) {
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]85 idt[i].access = 0x8e;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]86 idt[i].res = 0;
87 idt[i].selector = 0x10;
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]88 set_vector(i, irq_entry);
89 irq_entry += irq_entry_size;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]90 }
91
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]92 idt_ptr.size = 256 * 8;
93 idt_ptr.address = (unsigned long) idt;
94 idt_ptr.segment = 0x18;
95
96 load_idt(&idt_ptr);
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]97
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]98 /* It is now safe to enable interrupts */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]99 enable_interrupts();
100
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]101 return 0;
102}
103
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]104void __do_irq(int irq)
105{
106 printf("Unhandled IRQ : %d\n", irq);
107}
108void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
109
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]110void enable_interrupts(void)
111{
112 asm("sti\n");
113}
114
115int disable_interrupts(void)
116{
117 long flags;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]118
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]119 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]120
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]121 return (flags&0x200); /* IE flags is bit 9 */
122}
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]123
124/* IRQ Low-Level Service Routine */
125__isr__ irq_llsr(int ip, int seg, int irq)
126{
127 /*
128 * For detailed description of each exception, refer to:
129 * Intel® 64 and IA-32 Architectures Software Developer's Manual
130 * Volume 1: Basic Architecture
131 * Order Number: 253665-029US, November 2008
132 * Table 6-1. Exceptions and Interrupts
133 */
134 switch (irq) {
135 case 0x00:
136 printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
137 while(1);
138 break;
139 case 0x01:
140 printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
141 break;
142 case 0x02:
143 printf("NMI Interrupt at %04x:%08x\n", seg, ip);
144 break;
145 case 0x03:
146 printf("Breakpoint at %04x:%08x\n", seg, ip);
147 break;
148 case 0x04:
149 printf("Overflow at %04x:%08x\n", seg, ip);
150 while(1);
151 break;
152 case 0x05:
153 printf("BOUND Range Exceeded at %04x:%08x\n", seg, ip);
154 while(1);
155 break;
156 case 0x06:
157 printf("Invalid Opcode (UnDefined Opcode) at %04x:%08x\n", seg, ip);
158 while(1);
159 break;
160 case 0x07:
161 printf("Device Not Available (No Math Coprocessor) at %04x:%08x\n", seg, ip);
162 while(1);
163 break;
164 case 0x08:
165 printf("Double fault at %04x:%08x\n", seg, ip);
166 while(1);
167 break;
168 case 0x09:
169 printf("Co-processor segment overrun at %04x:%08x\n", seg, ip);
170 while(1);
171 break;
172 case 0x0a:
173 printf("Invalid TSS at %04x:%08x\n", seg, ip);
174 break;
175 case 0x0b:
176 printf("Segment Not Present at %04x:%08x\n", seg, ip);
177 while(1);
178 break;
179 case 0x0c:
180 printf("Stack Segment Fault at %04x:%08x\n", seg, ip);
181 while(1);
182 break;
183 case 0x0d:
184 printf("General Protection at %04x:%08x\n", seg, ip);
185 break;
186 case 0x0e:
187 printf("Page fault at %04x:%08x\n", seg, ip);
188 while(1);
189 break;
190 case 0x0f:
191 printf("Floating-Point Error (Math Fault) at %04x:%08x\n", seg, ip);
192 break;
193 case 0x10:
194 printf("Alignment check at %04x:%08x\n", seg, ip);
195 break;
196 case 0x11:
197 printf("Machine Check at %04x:%08x\n", seg, ip);
198 break;
199 case 0x12:
200 printf("SIMD Floating-Point Exception at %04x:%08x\n", seg, ip);
201 break;
202 case 0x13:
203 case 0x14:
204 case 0x15:
205 case 0x16:
206 case 0x17:
207 case 0x18:
208 case 0x19:
209 case 0x1a:
210 case 0x1b:
211 case 0x1c:
212 case 0x1d:
213 case 0x1e:
214 case 0x1f:
215 printf("Reserved Exception %d at %04x:%08x\n", irq, seg, ip);
216 break;
217
218 default:
219 /* Hardware or User IRQ */
220 do_irq(irq);
221 }
222}
223
224/*
225 * OK - This looks really horrible, but it serves a purpose - It helps create
226 * fully relocatable code.
227 * - The call to irq_llsr will be a relative jump
228 * - The IRQ entries will be guaranteed to be in order
229 * It's a bit annoying that we need to waste 3 bytes per interrupt entry
230 * (total of 768 code bytes), but we MUST create a Stack Frame and this is
231 * the easiest way I could do it. Maybe it can be made better later.
232 */
233asm(".globl irq_common_entry\n" \
Graeme Russ0fc1b492009-11-24 20:04:19 +1100[diff] [blame]234 ".hidden irq_common_entry\n" \
235 ".type irq_common_entry, @function\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]236 "irq_common_entry:\n" \
237 "pushl $0\n" \
238 "pushl $0\n" \
239 "call irq_llsr\n" \
240 "popl %eax\n" \
241 "popl %eax\n" \
242 "popl %eax\n" \
243 "popa\n" \
244 "leave\n"\
245 "iret\n" \
246 DECLARE_INTERRUPT(0) \
247 DECLARE_INTERRUPT(1) \
248 DECLARE_INTERRUPT(2) \
249 DECLARE_INTERRUPT(3) \
250 DECLARE_INTERRUPT(4) \
251 DECLARE_INTERRUPT(5) \
252 DECLARE_INTERRUPT(6) \
253 DECLARE_INTERRUPT(7) \
254 DECLARE_INTERRUPT(8) \
255 DECLARE_INTERRUPT(9) \
256 DECLARE_INTERRUPT(10) \
257 DECLARE_INTERRUPT(11) \
258 DECLARE_INTERRUPT(12) \
259 DECLARE_INTERRUPT(13) \
260 DECLARE_INTERRUPT(14) \
261 DECLARE_INTERRUPT(15) \
262 DECLARE_INTERRUPT(16) \
263 DECLARE_INTERRUPT(17) \
264 DECLARE_INTERRUPT(18) \
265 DECLARE_INTERRUPT(19) \
266 DECLARE_INTERRUPT(20) \
267 DECLARE_INTERRUPT(21) \
268 DECLARE_INTERRUPT(22) \
269 DECLARE_INTERRUPT(23) \
270 DECLARE_INTERRUPT(24) \
271 DECLARE_INTERRUPT(25) \
272 DECLARE_INTERRUPT(26) \
273 DECLARE_INTERRUPT(27) \
274 DECLARE_INTERRUPT(28) \
275 DECLARE_INTERRUPT(29) \
276 DECLARE_INTERRUPT(30) \
277 DECLARE_INTERRUPT(31) \
278 DECLARE_INTERRUPT(32) \
279 DECLARE_INTERRUPT(33) \
280 DECLARE_INTERRUPT(34) \
281 DECLARE_INTERRUPT(35) \
282 DECLARE_INTERRUPT(36) \
283 DECLARE_INTERRUPT(37) \
284 DECLARE_INTERRUPT(38) \
285 DECLARE_INTERRUPT(39) \
286 DECLARE_INTERRUPT(40) \
287 DECLARE_INTERRUPT(41) \
288 DECLARE_INTERRUPT(42) \
289 DECLARE_INTERRUPT(43) \
290 DECLARE_INTERRUPT(44) \
291 DECLARE_INTERRUPT(45) \
292 DECLARE_INTERRUPT(46) \
293 DECLARE_INTERRUPT(47) \
294 DECLARE_INTERRUPT(48) \
295 DECLARE_INTERRUPT(49) \
296 DECLARE_INTERRUPT(50) \
297 DECLARE_INTERRUPT(51) \
298 DECLARE_INTERRUPT(52) \
299 DECLARE_INTERRUPT(53) \
300 DECLARE_INTERRUPT(54) \
301 DECLARE_INTERRUPT(55) \
302 DECLARE_INTERRUPT(56) \
303 DECLARE_INTERRUPT(57) \
304 DECLARE_INTERRUPT(58) \
305 DECLARE_INTERRUPT(59) \
306 DECLARE_INTERRUPT(60) \
307 DECLARE_INTERRUPT(61) \
308 DECLARE_INTERRUPT(62) \
309 DECLARE_INTERRUPT(63) \
310 DECLARE_INTERRUPT(64) \
311 DECLARE_INTERRUPT(65) \
312 DECLARE_INTERRUPT(66) \
313 DECLARE_INTERRUPT(67) \
314 DECLARE_INTERRUPT(68) \
315 DECLARE_INTERRUPT(69) \
316 DECLARE_INTERRUPT(70) \
317 DECLARE_INTERRUPT(71) \
318 DECLARE_INTERRUPT(72) \
319 DECLARE_INTERRUPT(73) \
320 DECLARE_INTERRUPT(74) \
321 DECLARE_INTERRUPT(75) \
322 DECLARE_INTERRUPT(76) \
323 DECLARE_INTERRUPT(77) \
324 DECLARE_INTERRUPT(78) \
325 DECLARE_INTERRUPT(79) \
326 DECLARE_INTERRUPT(80) \
327 DECLARE_INTERRUPT(81) \
328 DECLARE_INTERRUPT(82) \
329 DECLARE_INTERRUPT(83) \
330 DECLARE_INTERRUPT(84) \
331 DECLARE_INTERRUPT(85) \
332 DECLARE_INTERRUPT(86) \
333 DECLARE_INTERRUPT(87) \
334 DECLARE_INTERRUPT(88) \
335 DECLARE_INTERRUPT(89) \
336 DECLARE_INTERRUPT(90) \
337 DECLARE_INTERRUPT(91) \
338 DECLARE_INTERRUPT(92) \
339 DECLARE_INTERRUPT(93) \
340 DECLARE_INTERRUPT(94) \
341 DECLARE_INTERRUPT(95) \
342 DECLARE_INTERRUPT(97) \
343 DECLARE_INTERRUPT(96) \
344 DECLARE_INTERRUPT(98) \
345 DECLARE_INTERRUPT(99) \
346 DECLARE_INTERRUPT(100) \
347 DECLARE_INTERRUPT(101) \
348 DECLARE_INTERRUPT(102) \
349 DECLARE_INTERRUPT(103) \
350 DECLARE_INTERRUPT(104) \
351 DECLARE_INTERRUPT(105) \
352 DECLARE_INTERRUPT(106) \
353 DECLARE_INTERRUPT(107) \
354 DECLARE_INTERRUPT(108) \
355 DECLARE_INTERRUPT(109) \
356 DECLARE_INTERRUPT(110) \
357 DECLARE_INTERRUPT(111) \
358 DECLARE_INTERRUPT(112) \
359 DECLARE_INTERRUPT(113) \
360 DECLARE_INTERRUPT(114) \
361 DECLARE_INTERRUPT(115) \
362 DECLARE_INTERRUPT(116) \
363 DECLARE_INTERRUPT(117) \
364 DECLARE_INTERRUPT(118) \
365 DECLARE_INTERRUPT(119) \
366 DECLARE_INTERRUPT(120) \
367 DECLARE_INTERRUPT(121) \
368 DECLARE_INTERRUPT(122) \
369 DECLARE_INTERRUPT(123) \
370 DECLARE_INTERRUPT(124) \
371 DECLARE_INTERRUPT(125) \
372 DECLARE_INTERRUPT(126) \
373 DECLARE_INTERRUPT(127) \
374 DECLARE_INTERRUPT(128) \
375 DECLARE_INTERRUPT(129) \
376 DECLARE_INTERRUPT(130) \
377 DECLARE_INTERRUPT(131) \
378 DECLARE_INTERRUPT(132) \
379 DECLARE_INTERRUPT(133) \
380 DECLARE_INTERRUPT(134) \
381 DECLARE_INTERRUPT(135) \
382 DECLARE_INTERRUPT(136) \
383 DECLARE_INTERRUPT(137) \
384 DECLARE_INTERRUPT(138) \
385 DECLARE_INTERRUPT(139) \
386 DECLARE_INTERRUPT(140) \
387 DECLARE_INTERRUPT(141) \
388 DECLARE_INTERRUPT(142) \
389 DECLARE_INTERRUPT(143) \
390 DECLARE_INTERRUPT(144) \
391 DECLARE_INTERRUPT(145) \
392 DECLARE_INTERRUPT(146) \
393 DECLARE_INTERRUPT(147) \
394 DECLARE_INTERRUPT(148) \
395 DECLARE_INTERRUPT(149) \
396 DECLARE_INTERRUPT(150) \
397 DECLARE_INTERRUPT(151) \
398 DECLARE_INTERRUPT(152) \
399 DECLARE_INTERRUPT(153) \
400 DECLARE_INTERRUPT(154) \
401 DECLARE_INTERRUPT(155) \
402 DECLARE_INTERRUPT(156) \
403 DECLARE_INTERRUPT(157) \
404 DECLARE_INTERRUPT(158) \
405 DECLARE_INTERRUPT(159) \
406 DECLARE_INTERRUPT(160) \
407 DECLARE_INTERRUPT(161) \
408 DECLARE_INTERRUPT(162) \
409 DECLARE_INTERRUPT(163) \
410 DECLARE_INTERRUPT(164) \
411 DECLARE_INTERRUPT(165) \
412 DECLARE_INTERRUPT(166) \
413 DECLARE_INTERRUPT(167) \
414 DECLARE_INTERRUPT(168) \
415 DECLARE_INTERRUPT(169) \
416 DECLARE_INTERRUPT(170) \
417 DECLARE_INTERRUPT(171) \
418 DECLARE_INTERRUPT(172) \
419 DECLARE_INTERRUPT(173) \
420 DECLARE_INTERRUPT(174) \
421 DECLARE_INTERRUPT(175) \
422 DECLARE_INTERRUPT(176) \
423 DECLARE_INTERRUPT(177) \
424 DECLARE_INTERRUPT(178) \
425 DECLARE_INTERRUPT(179) \
426 DECLARE_INTERRUPT(180) \
427 DECLARE_INTERRUPT(181) \
428 DECLARE_INTERRUPT(182) \
429 DECLARE_INTERRUPT(183) \
430 DECLARE_INTERRUPT(184) \
431 DECLARE_INTERRUPT(185) \
432 DECLARE_INTERRUPT(186) \
433 DECLARE_INTERRUPT(187) \
434 DECLARE_INTERRUPT(188) \
435 DECLARE_INTERRUPT(189) \
436 DECLARE_INTERRUPT(190) \
437 DECLARE_INTERRUPT(191) \
438 DECLARE_INTERRUPT(192) \
439 DECLARE_INTERRUPT(193) \
440 DECLARE_INTERRUPT(194) \
441 DECLARE_INTERRUPT(195) \
442 DECLARE_INTERRUPT(196) \
443 DECLARE_INTERRUPT(197) \
444 DECLARE_INTERRUPT(198) \
445 DECLARE_INTERRUPT(199) \
446 DECLARE_INTERRUPT(200) \
447 DECLARE_INTERRUPT(201) \
448 DECLARE_INTERRUPT(202) \
449 DECLARE_INTERRUPT(203) \
450 DECLARE_INTERRUPT(204) \
451 DECLARE_INTERRUPT(205) \
452 DECLARE_INTERRUPT(206) \
453 DECLARE_INTERRUPT(207) \
454 DECLARE_INTERRUPT(208) \
455 DECLARE_INTERRUPT(209) \
456 DECLARE_INTERRUPT(210) \
457 DECLARE_INTERRUPT(211) \
458 DECLARE_INTERRUPT(212) \
459 DECLARE_INTERRUPT(213) \
460 DECLARE_INTERRUPT(214) \
461 DECLARE_INTERRUPT(215) \
462 DECLARE_INTERRUPT(216) \
463 DECLARE_INTERRUPT(217) \
464 DECLARE_INTERRUPT(218) \
465 DECLARE_INTERRUPT(219) \
466 DECLARE_INTERRUPT(220) \
467 DECLARE_INTERRUPT(221) \
468 DECLARE_INTERRUPT(222) \
469 DECLARE_INTERRUPT(223) \
470 DECLARE_INTERRUPT(224) \
471 DECLARE_INTERRUPT(225) \
472 DECLARE_INTERRUPT(226) \
473 DECLARE_INTERRUPT(227) \
474 DECLARE_INTERRUPT(228) \
475 DECLARE_INTERRUPT(229) \
476 DECLARE_INTERRUPT(230) \
477 DECLARE_INTERRUPT(231) \
478 DECLARE_INTERRUPT(232) \
479 DECLARE_INTERRUPT(233) \
480 DECLARE_INTERRUPT(234) \
481 DECLARE_INTERRUPT(235) \
482 DECLARE_INTERRUPT(236) \
483 DECLARE_INTERRUPT(237) \
484 DECLARE_INTERRUPT(238) \
485 DECLARE_INTERRUPT(239) \
486 DECLARE_INTERRUPT(240) \
487 DECLARE_INTERRUPT(241) \
488 DECLARE_INTERRUPT(242) \
489 DECLARE_INTERRUPT(243) \
490 DECLARE_INTERRUPT(244) \
491 DECLARE_INTERRUPT(245) \
492 DECLARE_INTERRUPT(246) \
493 DECLARE_INTERRUPT(247) \
494 DECLARE_INTERRUPT(248) \
495 DECLARE_INTERRUPT(249) \
496 DECLARE_INTERRUPT(250) \
497 DECLARE_INTERRUPT(251) \
498 DECLARE_INTERRUPT(252) \
499 DECLARE_INTERRUPT(253) \
500 DECLARE_INTERRUPT(254) \
501 DECLARE_INTERRUPT(255));