Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / bb3e5aa2896d69a6fe86861004d7d4e33824efbe / . / drivers / clk / sunxi / clk_h3.c
blob: 416aec2b897f360458706aedc6ba81bb66dd6b4e [file] [log] [blame]
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun8i-h3-ccu.h>
13#include <dt-bindings/reset/sun8i-h3-ccu.h>
14
15static struct ccu_clk_gate h3_gates[] = {
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame^]16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]19 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
20 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
21 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
22 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
23 [CLK_BUS_EHCI3] = GATE(0x060, BIT(27)),
24 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
25 [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
26 [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
27 [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
28
Jagan Teki4acc7112018-12-30 21:29:24 +0530[diff] [blame]29 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
30 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
31 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
32 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
33
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]34 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
35 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
36 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
37 [CLK_USB_PHY3] = GATE(0x0cc, BIT(11)),
38 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
39 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
40 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
41 [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)),
42};
43
44static struct ccu_reset h3_resets[] = {
45 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
46 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
47 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
48 [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
49
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame^]50 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
51 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
52 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]53 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
54 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
55 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
56 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(26)),
57 [RST_BUS_EHCI3] = RESET(0x2c0, BIT(27)),
58 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
59 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
60 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
61 [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
Jagan Teki8606f962018-12-30 21:37:31 +0530[diff] [blame]62
63 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
64 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
65 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
66 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]67};
68
69static const struct ccu_desc h3_ccu_desc = {
70 .gates = h3_gates,
71 .resets = h3_resets,
72};
73
74static int h3_clk_bind(struct udevice *dev)
75{
76 return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
77}
78
79static const struct udevice_id h3_ccu_ids[] = {
80 { .compatible = "allwinner,sun8i-h3-ccu",
81 .data = (ulong)&h3_ccu_desc },
82 { .compatible = "allwinner,sun50i-h5-ccu",
83 .data = (ulong)&h3_ccu_desc },
84 { }
85};
86
87U_BOOT_DRIVER(clk_sun8i_h3) = {
88 .name = "sun8i_h3_ccu",
89 .id = UCLASS_CLK,
90 .of_match = h3_ccu_ids,
91 .priv_auto_alloc_size = sizeof(struct ccu_priv),
92 .ops = &sunxi_clk_ops,
93 .probe = sunxi_clk_probe,
94 .bind = h3_clk_bind,
95};