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Wolfgang Denk70a20472005-09-25 15:59:01 +02001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Copied from lubbock.h
10 *
11 * (C) Copyright 2004
12 * BEC Systems <http://bec-systems.com>
13 * Cliff Brake <cliff.brake@gmail.com>
14 * Configuation settings for the Accelent/Vibren PXA255 IDP
15 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020016 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk70a20472005-09-25 15:59:01 +020017 */
18
19#ifndef __CONFIG_H
20#define __CONFIG_H
21
22#include <asm/arch/pxa-regs.h>
23
24/*
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020025 * If we are developing, we might want to start U-Boot from RAM
Wolfgang Denk70a20472005-09-25 15:59:01 +020026 * so we MUST NOT initialize critical regs like mem-timing ...
27 */
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020028#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
Marek Vasut65bd6a92010-10-20 21:20:07 +020029#define CONFIG_SYS_TEXT_BASE 0x0
Wolfgang Denk70a20472005-09-25 15:59:01 +020030
31/*
32 * define the following to enable debug blinks. A debug blink function
33 * must be defined in memsetup.S
34 */
35#undef DEBUG_BLINK_ENABLE
36#undef DEBUG_BLINKC_ENABLE
37
38/*
39 * High Level Configuration Options
40 * (easy to change)
41 */
Marek Vasutabc20ab2011-11-26 07:20:07 +010042#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */
Wolfgang Denk70a20472005-09-25 15:59:01 +020043
44#undef CONFIG_LCD
45#ifdef CONFIG_LCD
Jeroen Hofstee06980952013-01-22 10:44:10 +000046#define CONFIG_PXA_LCD
Wolfgang Denk70a20472005-09-25 15:59:01 +020047#define CONFIG_SHARP_LM8V31
48#endif
49
50#define CONFIG_MMC 1
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020051#define CONFIG_DOS_PARTITION 1
Helmut Raiger9660e442011-10-20 04:19:47 +000052#define CONFIG_BOARD_LATE_INIT
Wolfgang Denk70a20472005-09-25 15:59:01 +020053
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020054/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000055#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020056
Wolfgang Denk70a20472005-09-25 15:59:01 +020057/*
58 * Size of malloc() pool
59 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
Wolfgang Denk70a20472005-09-25 15:59:01 +020061
62/*
63 * PXA250 IDP memory map information
64 */
65
66#define IDP_CS5_ETH_OFFSET 0x03400000
67
68
69/*
70 * Hardware drivers
71 */
Ben Warren7194ab82009-10-04 22:37:03 -070072#define CONFIG_SMC91111
Wolfgang Denk70a20472005-09-25 15:59:01 +020073#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
74#define CONFIG_SMC_USE_32_BIT 1
75/* #define CONFIG_SMC_USE_IOFUNCS */
76
77/* the following has to be set high -- suspect something is wrong with
78 * with the tftp timeout routines. FIXME!!!
79 */
80#define CONFIG_NET_RETRY_COUNT 100
81
82/*
83 * select serial console configuration
84 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020085#define CONFIG_PXA_SERIAL
Wolfgang Denk70a20472005-09-25 15:59:01 +020086#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
Marek Vasutce6971c2012-09-12 12:36:25 +020087#define CONFIG_CONS_INDEX 3
Wolfgang Denk70a20472005-09-25 15:59:01 +020088
89/* allow to overwrite serial and ethaddr */
90#define CONFIG_ENV_OVERWRITE
91
92#define CONFIG_BAUDRATE 115200
93
Wolfgang Denk70a20472005-09-25 15:59:01 +020094
Jon Loeliger26a34562007-07-04 22:33:17 -050095/*
Jon Loeliger079a1362007-07-10 10:12:10 -050096 * BOOTP options
97 */
98#define CONFIG_BOOTP_BOOTFILESIZE
99#define CONFIG_BOOTP_BOOTPATH
100#define CONFIG_BOOTP_GATEWAY
101#define CONFIG_BOOTP_HOSTNAME
102
103
104/*
Jon Loeliger26a34562007-07-04 22:33:17 -0500105 * Command line configuration.
106 */
Jon Loeliger26a34562007-07-04 22:33:17 -0500107#define CONFIG_CMD_FAT
108#define CONFIG_CMD_DHCP
109
Wolfgang Denk70a20472005-09-25 15:59:01 +0200110#define CONFIG_BOOTDELAY 3
111#define CONFIG_BOOTCOMMAND "bootm 40000"
112#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
Wolfgang Denk25dbe982008-07-13 23:07:35 +0200113
114#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
115#define CONFIG_SETUP_MEMORY_TAGS 1
116/* #define CONFIG_INITRD_TAG 1 */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200117
118/*
119 * Current memory map for Vibren supplied Linux images:
120 *
121 * Flash:
122 * 0 - 0x3ffff (size = 0x40000): bootloader
123 * 0x40000 - 0x13ffff (size = 0x100000): kernel
124 * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
125 *
126 * RAM:
127 * 0xa0008000 - kernel is loaded
128 * 0xa3000000 - Uboot runs (48MB into RAM)
129 *
130 */
131
132#define CONFIG_EXTRA_ENV_SETTINGS \
133 "prog_boot_mmc=" \
134 "mw.b 0xa0000000 0xff 0x40000; " \
135 "if mmcinit && " \
136 "fatload mmc 0 0xa0000000 u-boot.bin; " \
137 "then " \
138 "protect off 0x0 0x3ffff; " \
139 "erase 0x0 0x3ffff; " \
140 "cp.b 0xa0000000 0x0 0x40000; " \
141 "reset;" \
142 "fi\0" \
143 "prog_uzImage_mmc=" \
144 "mw.b 0xa0000000 0xff 0x100000; " \
145 "if mmcinit && " \
146 "fatload mmc 0 0xa0000000 uzImage; " \
147 "then " \
148 "protect off 0x40000 0xfffff; " \
149 "erase 0x40000 0xfffff; " \
150 "cp.b 0xa0000000 0x40000 0x100000; " \
151 "fi\0" \
152 "prog_jffs_mmc=" \
153 "mw.b 0xa0000000 0xff 0x1e00000; " \
154 "if mmcinit && " \
155 "fatload mmc 0 0xa0000000 root.jffs; " \
156 "then " \
157 "protect off 0x140000 0x1f3ffff; " \
158 "erase 0x140000 0x1f3ffff; " \
159 "cp.b 0xa0000000 0x140000 0x1e00000; " \
160 "fi\0" \
161 "boot_mmc=" \
162 "if mmcinit && " \
163 "fatload mmc 0 0xa1000000 uzImage && " \
164 "then " \
165 "bootm 0xa1000000; " \
166 "fi\0" \
167 "prog_boot_net=" \
168 "mw.b 0xa0000000 0xff 0x100000; " \
169 "if bootp 0xa0000000 u-boot.bin; " \
170 "then " \
171 "protect off 0x0 0x3ffff; " \
172 "erase 0x0 0x3ffff; " \
173 "cp.b 0xa0000000 0x0 0x40000; " \
174 "reset; " \
175 "fi\0" \
176 "prog_uzImage_net=" \
177 "mw.b 0xa0000000 0xff 0x100000; " \
178 "if bootp 0xa0000000 uzImage; " \
179 "then " \
180 "protect off 0x40000 0xfffff; " \
181 "erase 0x40000 0xfffff; " \
182 "cp.b 0xa0000000 0x40000 0x100000; " \
183 "fi\0" \
184 "prog_jffs_net=" \
185 "mw.b 0xa0000000 0xff 0x1e00000; " \
186 "if bootp 0xa0000000 root.jffs; " \
187 "then " \
188 "protect off 0x140000 0x1f3ffff; " \
189 "erase 0x140000 0x1f3ffff; " \
190 "cp.b 0xa0000000 0x140000 0x1e00000; " \
191 "fi\0"
192
193
194/* "erase_env=" */
195/* "protect off" */
196
197
Jon Loeliger26a34562007-07-04 22:33:17 -0500198#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk70a20472005-09-25 15:59:01 +0200199#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200200#endif
201
202/*
203 * Miscellaneous configurable options
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_HUSH_PARSER 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_LONGHELP /* undef to save memory */
Nikita Kiryanov181bd9d2015-08-03 12:36:58 +0300208#undef CONFIG_SYS_PROMPT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#ifdef CONFIG_SYS_HUSH_PARSER
210#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200211#else
Wolfgang Denk70a20472005-09-25 15:59:01 +0200212#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
214#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
215#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
216#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
217#define CONFIG_SYS_DEVICE_NULLDEV 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
220#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200225
226#define RTC 1 /* enable 32KHz osc */
227
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100228#ifdef CONFIG_MMC
Marek Vasut831f8492012-09-30 10:09:49 +0000229#define CONFIG_GENERIC_MMC
230#define CONFIG_PXA_MMC_GENERIC
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100231#define CONFIG_CMD_MMC
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_MMC_BASE 0xF0000000
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100233#endif
Wolfgang Denk70a20472005-09-25 15:59:01 +0200234
235/*
Wolfgang Denk70a20472005-09-25 15:59:01 +0200236 * Physical Memory Map
237 */
Marek Vasut65bd6a92010-10-20 21:20:07 +0200238#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200239#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
240#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
241#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
242#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
243#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
244#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
245#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
246#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
247
248#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
249#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
250#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
251#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
252#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_DRAM_BASE 0xa0000000
255#define CONFIG_SYS_DRAM_SIZE 0x04000000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200256
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200258
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200259#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Marek Vasut00d5ec92011-11-26 12:04:11 +0100260#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200261
Wolfgang Denk70a20472005-09-25 15:59:01 +0200262/*
263 * GPIO settings
264 */
265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_GAFR0_L_VAL 0x80001005
267#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
268#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
269#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
270#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
271#define CONFIG_SYS_GAFR2_U_VAL 0x2
272#define CONFIG_SYS_GPCR0_VAL 0x1800400
273#define CONFIG_SYS_GPCR1_VAL 0x0
274#define CONFIG_SYS_GPCR2_VAL 0x0
275#define CONFIG_SYS_GPDR0_VAL 0xc1818440
276#define CONFIG_SYS_GPDR1_VAL 0xfcffab82
277#define CONFIG_SYS_GPDR2_VAL 0x1ffff
278#define CONFIG_SYS_GPSR0_VAL 0x8000
279#define CONFIG_SYS_GPSR1_VAL 0x3f0002
280#define CONFIG_SYS_GPSR2_VAL 0x1c000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_PSSR_VAL 0x20
Wolfgang Denk70a20472005-09-25 15:59:01 +0200283
Marek Vasut65bd6a92010-10-20 21:20:07 +0200284#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
285#define CONFIG_SYS_CKEN 0x0
286
Wolfgang Denk70a20472005-09-25 15:59:01 +0200287/*
288 * Memory settings
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_MSC0_VAL 0x29DCA4D2
291#define CONFIG_SYS_MSC1_VAL 0x43AC494C
292#define CONFIG_SYS_MSC2_VAL 0x39D449D4
293#define CONFIG_SYS_MDCNFG_VAL 0x090009C9
294#define CONFIG_SYS_MDREFR_VAL 0x0085C017
295#define CONFIG_SYS_MDMRS_VAL 0x00220022
Marek Vasut65bd6a92010-10-20 21:20:07 +0200296#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
297#define CONFIG_SYS_SXCNFG_VAL 0x00000000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200298
299/*
300 * PCMCIA and CF Interfaces
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_MECR_VAL 0x00000003
303#define CONFIG_SYS_MCMEM0_VAL 0x00014405
304#define CONFIG_SYS_MCMEM1_VAL 0x00014405
305#define CONFIG_SYS_MCATT0_VAL 0x00014405
306#define CONFIG_SYS_MCATT1_VAL 0x00014405
307#define CONFIG_SYS_MCIO0_VAL 0x00014405
308#define CONFIG_SYS_MCIO1_VAL 0x00014405
Wolfgang Denk70a20472005-09-25 15:59:01 +0200309
310/*
311 * FLASH and environment organization
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200314#define CONFIG_FLASH_CFI_DRIVER 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_MONITOR_BASE 0
317#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
Wolfgang Denk70a20472005-09-25 15:59:01 +0200318
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
320#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200321
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200323
324/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
326#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200327
328/* put cfg at end of flash for now */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200329#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200330 /* Addr of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200331#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
332#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
333#define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16)
Wolfgang Denk70a20472005-09-25 15:59:01 +0200334
335#endif /* __CONFIG_H */