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Bartlomiej Sieka4707fb52006-10-13 21:09:09 +02001/*
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +01002 * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +02003 * wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020011/*
12 * High Level Configuration Options
13 * (easy to change)
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010014 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010015#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
16#define CONFIG_V38B 1 /* ...on V38B board */
Anatolij Gustschine1219222015-08-13 23:58:00 +020017#define CONFIG_SYS_GENERIC_BOARD
18#define CONFIG_DISPLAY_BOARDINFO
Wolfgang Denk2ae18242010-10-06 09:05:45 +020019
20#define CONFIG_SYS_TEXT_BASE 0xFF000000
21
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020023
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010024#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
25#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020026
Bartlomiej Siekace3f1a42006-11-11 22:48:22 +010027#undef CONFIG_HW_WATCHDOG /* don't use watchdog */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020028
29#define CONFIG_NETCONSOLE 1
30
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010031#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +010032#define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */
Mike Frysingerd8d21e62009-02-16 18:03:14 -050033#define CONFIG_MISC_INIT_R
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020034
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020036
Becky Bruce31d82672008-05-08 19:02:12 -050037#define CONFIG_HIGH_BATS 1 /* High BATs supported */
38
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020039/*
40 * Serial console configuration
41 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010042#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
43#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020045
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020046/*
47 * DDR
48 */
49#define SDRAM_DDR 1 /* is DDR */
50/* Settings for XLB = 132 MHz */
51#define SDRAM_MODE 0x018D0000
52#define SDRAM_EMODE 0x40090000
53#define SDRAM_CONTROL 0x704f0f00
54#define SDRAM_CONFIG1 0x73722930
55#define SDRAM_CONFIG2 0x47770000
56#define SDRAM_TAPDELAY 0x10000000
57
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020058/*
59 * PCI - no suport
60 */
61#undef CONFIG_PCI
62
63/*
64 * Partitions
65 */
66#define CONFIG_MAC_PARTITION 1
67#define CONFIG_DOS_PARTITION 1
68
69/*
70 * USB
71 */
72#define CONFIG_USB_OHCI
73#define CONFIG_USB_STORAGE
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010074#define CONFIG_USB_CLOCK 0x0001BBBB
75#define CONFIG_USB_CONFIG 0x00001000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020076
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050077
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020078/*
Jon Loeliger079a1362007-07-10 10:12:10 -050079 * BOOTP options
80 */
81#define CONFIG_BOOTP_BOOTFILESIZE
82#define CONFIG_BOOTP_BOOTPATH
83#define CONFIG_BOOTP_GATEWAY
84#define CONFIG_BOOTP_HOSTNAME
85
86
87/*
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050088 * Command line configuration.
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020089 */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050090#define CONFIG_CMD_FAT
91#define CONFIG_CMD_I2C
92#define CONFIG_CMD_IDE
93#define CONFIG_CMD_PING
94#define CONFIG_CMD_DHCP
95#define CONFIG_CMD_DIAG
96#define CONFIG_CMD_IRQ
97#define CONFIG_CMD_JFFS2
98#define CONFIG_CMD_MII
99#define CONFIG_CMD_SDRAM
100#define CONFIG_CMD_DATE
101#define CONFIG_CMD_USB
102#define CONFIG_CMD_FAT
103
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200104
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100105#define CONFIG_TIMESTAMP /* Print image info with timestamp */
106
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200107/*
108 * Boot low with 16 MB Flash
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_LOWBOOT 1
111#define CONFIG_SYS_LOWBOOT16 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200112
113/*
114 * Autobooting
115 */
116#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
117
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100118#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100119 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200120 "echo"
121
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100122#undef CONFIG_BOOTARGS
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200123
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200124#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200125 "bootcmd=run net_nfs\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100126 "bootdelay=3\0" \
127 "baudrate=115200\0" \
128 "preboot=echo;echo Type \"run flash_nfs\" to mount root " \
129 "filesystem over NFS; echo\0" \
130 "netdev=eth0\0" \
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +0100131 "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200132 "addip=setenv bootargs $(bootargs) " \
133 "ip=$(ipaddr):$(serverip):$(gatewayip):" \
134 "$(netmask):$(hostname):$(netdev):off panic=1\0" \
135 "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
136 "flash_self=run ramargs addip;bootm $(kernel_addr) " \
137 "$(ramdisk_addr)\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100138 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200139 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +0100140 "nfsroot=$(serverip):$(rootpath) wdt=off\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100141 "hostname=v38b\0" \
Heiko Schocher48690d82010-07-20 17:45:02 +0200142 "ethact=FEC\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100143 "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
144 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
145 "cp.b 200000 ff000000 $(filesize);" \
146 "prot on ff000000 ff03ffff\0" \
147 "load=tftp 200000 $(u-boot)\0" \
148 "netmask=255.255.0.0\0" \
149 "ipaddr=192.168.160.18\0" \
150 "serverip=192.168.1.1\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100151 "bootfile=/tftpboot/v38b/uImage\0" \
152 "u-boot=/tftpboot/v38b/u-boot.bin\0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200153 ""
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200154
155#define CONFIG_BOOTCOMMAND "run net_nfs"
156
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200157/*
158 * IPB Bus clocking configuration.
159 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100161
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200162/*
163 * I2C configuration
164 */
165#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
167#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
168#define CONFIG_SYS_I2C_SLAVE 0x7F
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200169
170/*
171 * EEPROM configuration
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
174#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
175#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
176#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200177
178/*
179 * RTC configuration
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_I2C_RTC_ADDR 0x51
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200182
183/*
184 * Flash configuration - use CFI driver
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200187#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
189#define CONFIG_SYS_FLASH_BASE 0xFF000000
190#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
191#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
192#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */
193#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
194#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200195
196/*
197 * Environment settings
198 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200199#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200201#define CONFIG_ENV_SIZE 0x10000
202#define CONFIG_ENV_SECT_SIZE 0x10000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200203#define CONFIG_ENV_OVERWRITE 1
204
205/*
206 * Memory map
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_MBAR 0xF0000000
209#define CONFIG_SYS_SDRAM_BASE 0x00000000
210#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200211
212/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200214#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200215
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200216#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200218
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200219#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
221# define CONFIG_SYS_RAMBOOT 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200222#endif
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
225#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
226#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200227
228/*
229 * Ethernet configuration
230 */
231#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800232#define CONFIG_MPC5xxx_FEC_MII100
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200233#define CONFIG_PHY_ADDR 0x00
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200234#define CONFIG_MII 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200235
236/*
237 * GPIO configuration
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200240
241/*
242 * Miscellaneous configurable options
243 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500245#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200247#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200249#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
251#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
252#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
255#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200256
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500260#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500262#endif
263
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200264/*
265 * Various low-level settings
266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
268#define CONFIG_SYS_HID0_FINAL HID0_ICE
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
271#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
272#define CONFIG_SYS_BOOTCS_CFG 0x00047801
273#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
274#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_CS_BURST 0x00000000
277#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200280
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100281/*
282 * IDE/ATA (supports IDE harddisk)
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200283 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100284#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
285#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
286#undef CONFIG_IDE_LED /* LED for ide not supported */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200287
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100288#define CONFIG_IDE_RESET /* reset for ide supported */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200289#define CONFIG_IDE_PREINIT
290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
292#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200305
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100306/*
307 * Status LED
308 */
309#define CONFIG_STATUS_LED /* Status LED enabled */
310#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200311
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200313#ifndef __ASSEMBLY__
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200314typedef unsigned int led_id_t;
315
316#define __led_toggle(_msk) \
317 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318 *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200319 } while(0)
320
321#define __led_set(_msk, _st) \
322 do { \
323 if ((_st)) \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324 *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200325 else \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200327 } while(0)
328
329#define __led_init(_msk, st) \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100330 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100332 } while(0)
333#endif /* __ASSEMBLY__ */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200334
335#endif /* __CONFIG_H */