blob: 1c74e97c5e9d955de8b21bf2cb99735f9a877231 [file] [log] [blame]
Anatolij Gustschinbed53752008-01-11 14:30:01 +01001/*
2 * (C) Copyright 2007
3 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Anatolij Gustschinbed53752008-01-11 14:30:01 +01006 */
7
8/*
9 * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
10 * PCI and video mode code was derived from smiLynxEM driver.
11 */
12
13#include <common.h>
14
Anatolij Gustschinbed53752008-01-11 14:30:01 +010015#include <asm/io.h>
16#include <pci.h>
17#include <video_fb.h>
18#include "videomodes.h"
19#include <mb862xx.h>
20
Yuri Tikhonov0d489262008-03-24 11:30:54 +010021#if defined(CONFIG_POST)
22#include <post.h>
23#endif
Anatolij Gustschine8652862009-07-07 13:24:08 +020024
Anatolij Gustschinbed53752008-01-11 14:30:01 +010025/*
26 * Graphic Device
27 */
28GraphicDevice mb862xx;
29
30/*
31 * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
32 */
33#define VIDEO_MEM_SIZE 0x01FC0000
34
35#if defined(CONFIG_PCI)
36#if defined(CONFIG_VIDEO_CORALP)
37
38static struct pci_device_id supported[] = {
39 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
40 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
41 { }
42};
43
44/* Internal clock frequency divider table, index is mode number */
45unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
46#endif
47#endif
48
49#if defined(CONFIG_VIDEO_CORALP)
50#define rd_io in32r
51#define wr_io out32r
52#else
Anatolij Gustschine8652862009-07-07 13:24:08 +020053#define rd_io(addr) in_be32((volatile unsigned *)(addr))
54#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
Anatolij Gustschinbed53752008-01-11 14:30:01 +010055#endif
56
Anatolij Gustschincce99b22009-07-07 13:27:07 +020057#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
58#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
Anatolij Gustschine8652862009-07-07 13:24:08 +020059 (val))
Anatolij Gustschincce99b22009-07-07 13:27:07 +020060#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
61#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
Anatolij Gustschine8652862009-07-07 13:24:08 +020062 (val))
63#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
64#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
Anatolij Gustschinbed53752008-01-11 14:30:01 +010065
66#if defined(CONFIG_VIDEO_CORALP)
Anatolij Gustschincce99b22009-07-07 13:27:07 +020067#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
Anatolij Gustschinbed53752008-01-11 14:30:01 +010068#else
Anatolij Gustschincce99b22009-07-07 13:27:07 +020069#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
Anatolij Gustschinbed53752008-01-11 14:30:01 +010070#endif
71
Anatolij Gustschincce99b22009-07-07 13:27:07 +020072#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
73 (GC_DISP_BASE | GC_L0PAL0) + \
Anatolij Gustschine8652862009-07-07 13:24:08 +020074 ((idx) << 2)), (val))
Anatolij Gustschinbed53752008-01-11 14:30:01 +010075
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +020076#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
Anatolij Gustschine8652862009-07-07 13:24:08 +020077static void gdc_sw_reset (void)
Anatolij Gustschinbed53752008-01-11 14:30:01 +010078{
Anatolij Gustschine8652862009-07-07 13:24:08 +020079 GraphicDevice *dev = &mb862xx;
80
Anatolij Gustschincce99b22009-07-07 13:27:07 +020081 HOST_WR_REG (GC_SRST, 0x1);
Anatolij Gustschinbed53752008-01-11 14:30:01 +010082 udelay (500);
83 video_hw_init ();
84}
85
86
Anatolij Gustschine8652862009-07-07 13:24:08 +020087static void de_wait (void)
Anatolij Gustschinbed53752008-01-11 14:30:01 +010088{
Anatolij Gustschine8652862009-07-07 13:24:08 +020089 GraphicDevice *dev = &mb862xx;
Anatolij Gustschinbed53752008-01-11 14:30:01 +010090 int lc = 0x10000;
91
Anatolij Gustschine8652862009-07-07 13:24:08 +020092 /*
93 * Sync with software writes to framebuffer,
94 * try to reset if engine locked
95 */
Anatolij Gustschincce99b22009-07-07 13:27:07 +020096 while (DE_RD_REG (GC_CTR) & 0x00000131)
Anatolij Gustschinbed53752008-01-11 14:30:01 +010097 if (lc-- < 0) {
98 gdc_sw_reset ();
Anatolij Gustschin9d173e02009-07-07 13:11:36 +020099 puts ("gdc reset done after drawing engine lock.\n");
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100100 break;
101 }
102}
103
Anatolij Gustschine8652862009-07-07 13:24:08 +0200104static void de_wait_slots (int slots)
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100105{
Anatolij Gustschine8652862009-07-07 13:24:08 +0200106 GraphicDevice *dev = &mb862xx;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100107 int lc = 0x10000;
108
109 /* Wait for free fifo slots */
Anatolij Gustschincce99b22009-07-07 13:27:07 +0200110 while (DE_RD_REG (GC_IFCNT) < slots)
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100111 if (lc-- < 0) {
112 gdc_sw_reset ();
Anatolij Gustschin9d173e02009-07-07 13:11:36 +0200113 puts ("gdc reset done after drawing engine lock.\n");
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100114 break;
115 }
116}
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +0200117#endif
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100118
119#if !defined(CONFIG_VIDEO_CORALP)
Anatolij Gustschine8652862009-07-07 13:24:08 +0200120static void board_disp_init (void)
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100121{
Anatolij Gustschine8652862009-07-07 13:24:08 +0200122 GraphicDevice *dev = &mb862xx;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100123 const gdc_regs *regs = board_get_regs ();
124
125 while (regs->index) {
126 DISP_WR_REG (regs->index, regs->value);
127 regs++;
128 }
129}
130#endif
131
132/*
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +0200133 * Init drawing engine if accel enabled.
134 * Also clears visible framebuffer.
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100135 */
136static void de_init (void)
137{
Anatolij Gustschine8652862009-07-07 13:24:08 +0200138 GraphicDevice *dev = &mb862xx;
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +0200139#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
Anatolij Gustschine8652862009-07-07 13:24:08 +0200140 int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100141
Anatolij Gustschincce99b22009-07-07 13:27:07 +0200142 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100143
144 /* Setup mode and fbbase, xres, fg, bg */
145 de_wait_slots (2);
146 DE_WR_FIFO (0xf1010108);
147 DE_WR_FIFO (cf | 0x0300);
Anatolij Gustschincce99b22009-07-07 13:27:07 +0200148 DE_WR_REG (GC_FBR, 0x0);
149 DE_WR_REG (GC_XRES, dev->winSizeX);
150 DE_WR_REG (GC_FC, 0x0);
151 DE_WR_REG (GC_BC, 0x0);
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100152 /* Reset clipping */
Anatolij Gustschincce99b22009-07-07 13:27:07 +0200153 DE_WR_REG (GC_CXMIN, 0x0);
154 DE_WR_REG (GC_CXMAX, dev->winSizeX);
155 DE_WR_REG (GC_CYMIN, 0x0);
156 DE_WR_REG (GC_CYMAX, dev->winSizeY);
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100157
158 /* Clear framebuffer using drawing engine */
159 de_wait_slots (3);
160 DE_WR_FIFO (0x09410000);
161 DE_WR_FIFO (0x00000000);
Anatolij Gustschine8652862009-07-07 13:24:08 +0200162 DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
Anatolij Gustschin322716a2008-07-12 17:31:36 +0200163 /* sync with SW access to framebuffer */
164 de_wait ();
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +0200165#else
166 unsigned int i, *p;
167
168 i = dev->winSizeX * dev->winSizeY;
169 p = (unsigned int *)dev->frameAdrs;
170 while (i--)
171 *p++ = 0;
172#endif
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100173}
174
175#if defined(CONFIG_VIDEO_CORALP)
Anatolij Gustschind7ffd272011-05-27 16:08:20 +0200176/* use CCF and MMR parameters for Coral-P Eval. Board as default */
177#ifndef CONFIG_SYS_MB862xx_CCF
178#define CONFIG_SYS_MB862xx_CCF 0x00090000
179#endif
180#ifndef CONFIG_SYS_MB862xx_MMR
181#define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
182#endif
183
Anatolij Gustschine8652862009-07-07 13:24:08 +0200184unsigned int pci_video_init (void)
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100185{
Anatolij Gustschine8652862009-07-07 13:24:08 +0200186 GraphicDevice *dev = &mb862xx;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100187 pci_dev_t devbusfn;
Anatolij Gustschind7ffd272011-05-27 16:08:20 +0200188 u16 device;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100189
Anatolij Gustschine8652862009-07-07 13:24:08 +0200190 if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
Anatolij Gustschin01b0f502011-07-16 22:28:23 +0200191 puts("controller not present\n");
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100192 return 0;
193 }
194
195 /* PCI setup */
Anatolij Gustschine8652862009-07-07 13:24:08 +0200196 pci_write_config_dword (devbusfn, PCI_COMMAND,
197 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
198 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
199 dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100200
Anatolij Gustschine8652862009-07-07 13:24:08 +0200201 if (dev->frameAdrs == 0) {
Anatolij Gustschin9d173e02009-07-07 13:11:36 +0200202 puts ("PCI config: failed to get base address\n");
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100203 return 0;
204 }
205
Anatolij Gustschine8652862009-07-07 13:24:08 +0200206 dev->pciBase = dev->frameAdrs;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100207
Anatolij Gustschind7ffd272011-05-27 16:08:20 +0200208 puts("Coral-");
209
210 pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
211 switch (device) {
212 case PCI_DEVICE_ID_CORAL_P:
213 puts("P\n");
214 break;
215 case PCI_DEVICE_ID_CORAL_PA:
216 puts("PA\n");
217 break;
218 default:
219 puts("Unknown\n");
220 return 0;
221 }
222
223 /* Setup clocks and memory mode for Coral-P(A) */
224 HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100225 udelay (200);
Anatolij Gustschind7ffd272011-05-27 16:08:20 +0200226 HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100227 udelay (100);
Anatolij Gustschine8652862009-07-07 13:24:08 +0200228 return dev->frameAdrs;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100229}
230
231unsigned int card_init (void)
232{
Anatolij Gustschine8652862009-07-07 13:24:08 +0200233 GraphicDevice *dev = &mb862xx;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100234 unsigned int cf, videomode, div = 0;
235 unsigned long t1, hsync, vsync;
236 char *penv;
237 int tmp, i, bpp;
238 struct ctfb_res_modes *res_mode;
239 struct ctfb_res_modes var_mode;
240
Anatolij Gustschine8652862009-07-07 13:24:08 +0200241 memset (dev, 0, sizeof (GraphicDevice));
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100242
Anatolij Gustschine8652862009-07-07 13:24:08 +0200243 if (!pci_video_init ())
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100244 return 0;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100245
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100246 tmp = 0;
247 videomode = 0x310;
248 /* get video mode via environment */
249 if ((penv = getenv ("videomode")) != NULL) {
Anatolij Gustschine8652862009-07-07 13:24:08 +0200250 /* decide if it is a string */
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100251 if (penv[0] <= '9') {
252 videomode = (int) simple_strtoul (penv, NULL, 16);
253 tmp = 1;
254 }
255 } else {
256 tmp = 1;
257 }
Anatolij Gustschine8652862009-07-07 13:24:08 +0200258
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100259 if (tmp) {
Anatolij Gustschine8652862009-07-07 13:24:08 +0200260 /* parameter are vesa modes, search params */
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100261 for (i = 0; i < VESA_MODES_COUNT; i++) {
262 if (vesa_modes[i].vesanr == videomode)
263 break;
264 }
265 if (i == VESA_MODES_COUNT) {
Anatolij Gustschine8652862009-07-07 13:24:08 +0200266 printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
267 videomode);
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100268 i = 0;
269 }
Anatolij Gustschine8652862009-07-07 13:24:08 +0200270 res_mode = (struct ctfb_res_modes *)
271 &res_mode_init[vesa_modes[i].resindex];
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100272 if (vesa_modes[i].resindex > 2) {
Anatolij Gustschin9d173e02009-07-07 13:11:36 +0200273 puts ("\tUnsupported resolution, using default\n");
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100274 bpp = vesa_modes[1].bits_per_pixel;
275 div = fr_div[1];
276 }
277 bpp = vesa_modes[i].bits_per_pixel;
278 div = fr_div[vesa_modes[i].resindex];
279 } else {
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100280 res_mode = (struct ctfb_res_modes *) &var_mode;
281 bpp = video_get_params (res_mode, penv);
282 }
283
284 /* calculate hsync and vsync freq (info only) */
285 t1 = (res_mode->left_margin + res_mode->xres +
286 res_mode->right_margin + res_mode->hsync_len) / 8;
287 t1 *= 8;
288 t1 *= res_mode->pixclock;
289 t1 /= 1000;
290 hsync = 1000000000L / t1;
291 t1 *= (res_mode->upper_margin + res_mode->yres +
292 res_mode->lower_margin + res_mode->vsync_len);
293 t1 /= 1000;
294 vsync = 1000000000L / t1;
295
296 /* fill in Graphic device struct */
Anatolij Gustschine8652862009-07-07 13:24:08 +0200297 sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100298 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
Anatolij Gustschine8652862009-07-07 13:24:08 +0200299 printf ("\t%s\n", dev->modeIdent);
300 dev->winSizeX = res_mode->xres;
301 dev->winSizeY = res_mode->yres;
302 dev->memSize = VIDEO_MEM_SIZE;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100303
304 switch (bpp) {
305 case 8:
Anatolij Gustschine8652862009-07-07 13:24:08 +0200306 dev->gdfIndex = GDF__8BIT_INDEX;
307 dev->gdfBytesPP = 1;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100308 break;
309 case 15:
310 case 16:
Anatolij Gustschine8652862009-07-07 13:24:08 +0200311 dev->gdfIndex = GDF_15BIT_555RGB;
312 dev->gdfBytesPP = 2;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100313 break;
314 default:
Anatolij Gustschine8652862009-07-07 13:24:08 +0200315 printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
316 bpp);
Anatolij Gustschin9d173e02009-07-07 13:11:36 +0200317 puts ("\tfallback to 15bpp\n");
Anatolij Gustschine8652862009-07-07 13:24:08 +0200318 dev->gdfIndex = GDF_15BIT_555RGB;
319 dev->gdfBytesPP = 2;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100320 }
321
322 /* Setup dot clock (internal pll, division rate) */
Anatolij Gustschincce99b22009-07-07 13:27:07 +0200323 DISP_WR_REG (GC_DCM1, div);
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100324 /* L0 init */
Anatolij Gustschine8652862009-07-07 13:24:08 +0200325 cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
Anatolij Gustschincce99b22009-07-07 13:27:07 +0200326 DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
Anatolij Gustschine8652862009-07-07 13:24:08 +0200327 (dev->winSizeY - 1) | cf);
Anatolij Gustschincce99b22009-07-07 13:27:07 +0200328 DISP_WR_REG (GC_L0OA0, 0x0);
329 DISP_WR_REG (GC_L0DA0, 0x0);
330 DISP_WR_REG (GC_L0DY_L0DX, 0x0);
331 DISP_WR_REG (GC_L0EM, 0x0);
332 DISP_WR_REG (GC_L0WY_L0WX, 0x0);
333 DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100334
335 /* Display timing init */
Anatolij Gustschincce99b22009-07-07 13:27:07 +0200336 DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
337 res_mode->left_margin +
338 res_mode->right_margin +
339 res_mode->hsync_len - 1) << 16);
340 DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
341 (dev->winSizeX - 1));
342 DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
343 (res_mode->hsync_len - 1) << 16 |
344 (dev->winSizeX +
345 res_mode->right_margin - 1));
346 DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
347 res_mode->upper_margin +
348 res_mode->vsync_len - 1) << 16);
349 DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
350 (dev->winSizeY +
351 res_mode->lower_margin - 1));
352 DISP_WR_REG (GC_WY_WX, 0x0);
353 DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100354 /* Display enable, L0 layer */
Anatolij Gustschincce99b22009-07-07 13:27:07 +0200355 DISP_WR_REG (GC_DCM1, 0x80010000 | div);
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100356
Anatolij Gustschine8652862009-07-07 13:24:08 +0200357 return dev->frameAdrs;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100358}
359#endif
360
Wolfgang Grandeggerc28d3bb2009-10-23 12:03:13 +0200361
362#if !defined(CONFIG_VIDEO_CORALP)
363int mb862xx_probe(unsigned int addr)
364{
365 GraphicDevice *dev = &mb862xx;
366 unsigned int reg;
367
368 dev->frameAdrs = addr;
369 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
370
371 /* Try to access GDC ID/Revision registers */
372 reg = HOST_RD_REG (GC_CID);
373 reg = HOST_RD_REG (GC_CID);
374 if (reg == 0x303) {
375 reg = DE_RD_REG(GC_REV);
376 reg = DE_RD_REG(GC_REV);
377 if ((reg & ~0xff) == 0x20050100)
378 return MB862XX_TYPE_LIME;
379 }
380
381 return 0;
382}
383#endif
384
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100385void *video_hw_init (void)
386{
Anatolij Gustschine8652862009-07-07 13:24:08 +0200387 GraphicDevice *dev = &mb862xx;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100388
Anatolij Gustschin9d173e02009-07-07 13:11:36 +0200389 puts ("Video: Fujitsu ");
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100390
Anatolij Gustschine8652862009-07-07 13:24:08 +0200391 memset (dev, 0, sizeof (GraphicDevice));
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100392
393#if defined(CONFIG_VIDEO_CORALP)
Anatolij Gustschine8652862009-07-07 13:24:08 +0200394 if (card_init () == 0)
395 return NULL;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100396#else
Anatolij Gustschine8652862009-07-07 13:24:08 +0200397 /*
398 * Preliminary init of the onboard graphic controller,
399 * retrieve base address
400 */
401 if ((dev->frameAdrs = board_video_init ()) == 0) {
Anatolij Gustschin9d173e02009-07-07 13:11:36 +0200402 puts ("Controller not found!\n");
Anatolij Gustschine8652862009-07-07 13:24:08 +0200403 return NULL;
Wolfgang Grandeggerc28d3bb2009-10-23 12:03:13 +0200404 } else {
Anatolij Gustschin9d173e02009-07-07 13:11:36 +0200405 puts ("Lime\n");
Wolfgang Grandeggerc28d3bb2009-10-23 12:03:13 +0200406
407 /* Set Change of Clock Frequency Register */
408 HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
409 /* Delay required */
410 udelay(300);
411 /* Set Memory I/F Mode Register) */
412 HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
413 }
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100414#endif
415
416 de_init ();
417
418#if !defined(CONFIG_VIDEO_CORALP)
Anatolij Gustschine8652862009-07-07 13:24:08 +0200419 board_disp_init ();
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100420#endif
421
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200422#if (defined(CONFIG_LWMON5) || \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423 defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100424 /* Lamp on */
425 board_backlight_switch (1);
426#endif
427
Anatolij Gustschine8652862009-07-07 13:24:08 +0200428 return dev;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100429}
430
431/*
432 * Set a RGB color in the LUT
433 */
Anatolij Gustschine8652862009-07-07 13:24:08 +0200434void video_set_lut (unsigned int index, unsigned char r,
435 unsigned char g, unsigned char b)
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100436{
Anatolij Gustschine8652862009-07-07 13:24:08 +0200437 GraphicDevice *dev = &mb862xx;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100438
439 L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
440}
441
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +0200442#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100443/*
444 * Drawing engine Fill and BitBlt screen region
445 */
Anatolij Gustschine8652862009-07-07 13:24:08 +0200446void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
447 unsigned int dst_y, unsigned int dim_x,
448 unsigned int dim_y, unsigned int color)
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100449{
Anatolij Gustschine8652862009-07-07 13:24:08 +0200450 GraphicDevice *dev = &mb862xx;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100451
452 de_wait_slots (3);
Anatolij Gustschincce99b22009-07-07 13:27:07 +0200453 DE_WR_REG (GC_FC, color);
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100454 DE_WR_FIFO (0x09410000);
455 DE_WR_FIFO ((dst_y << 16) | dst_x);
456 DE_WR_FIFO ((dim_y << 16) | dim_x);
457 de_wait ();
458}
459
Anatolij Gustschine8652862009-07-07 13:24:08 +0200460void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
461 unsigned int src_y, unsigned int dst_x,
462 unsigned int dst_y, unsigned int width,
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100463 unsigned int height)
464{
Anatolij Gustschine8652862009-07-07 13:24:08 +0200465 GraphicDevice *dev = &mb862xx;
Anatolij Gustschinbed53752008-01-11 14:30:01 +0100466 unsigned int ctrl = 0x0d000000L;
467
468 if (src_x >= dst_x && src_y >= dst_y)
469 ctrl |= 0x00440000L;
470 else if (src_x >= dst_x && src_y <= dst_y)
471 ctrl |= 0x00460000L;
472 else if (src_x <= dst_x && src_y >= dst_y)
473 ctrl |= 0x00450000L;
474 else
475 ctrl |= 0x00470000L;
476
477 de_wait_slots (4);
478 DE_WR_FIFO (ctrl);
479 DE_WR_FIFO ((src_y << 16) | src_x);
480 DE_WR_FIFO ((dst_y << 16) | dst_x);
481 DE_WR_FIFO ((height << 16) | width);
482 de_wait (); /* sync */
483}
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +0200484#endif