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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / bb8af5fb6acbca35a4f3ece2c0541ef52b315b76 / . / arch / arm / dts / k3-j721e-som-p0.dtsi
blob: 8497ff3e3e12cc5395a8fd0086776d88cdccf5f8 [file] [log] [blame]
Lokesh Vutla9a5e5532019-06-13 10:29:54 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j721e.dtsi"
9
10/ {
11 memory@80000000 {
12 device_type = "memory";
13 /* 4G RAM */
14 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
15 <0x00000008 0x80000000 0x00000000 0x80000000>;
16 };
17
18 reserved_memory: reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
21 ranges;
22
23 secure_ddr: optee@9e800000 {
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
26 no-map;
27 };
28 };
29};
Vignesh Raghavendra02e262c2019-10-23 13:30:03 +0530[diff] [blame]30
31&wkup_pmx0 {
32 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
33 pinctrl-single,pins = <
34 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
35 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
36 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
37 J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
38 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
39 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
40 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
41 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
42 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
43 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
44 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
45 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
46 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
47 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
48 >;
49 };
Vignesh Raghavendra224d7fe2020-02-04 11:09:52 +0530[diff] [blame]50
51 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
52 pinctrl-single,pins = <
53 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
54 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
55 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
56 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
57 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
58 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
59 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
60 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
61 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
62 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
63 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
64 >;
65 };
Vignesh Raghavendra02e262c2019-10-23 13:30:03 +0530[diff] [blame]66};
67
68&hbmc {
69 status = "disabled";
70 pinctrl-names = "default";
71 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
72 ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
73 <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
74
75 flash@0,0 {
76 compatible = "cypress,hyperflash", "cfi-flash";
77 reg = <0x0 0x0 0x4000000>;
78 };
79};
Vignesh Raghavendra224d7fe2020-02-04 11:09:52 +0530[diff] [blame]80
81&ospi0 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
84
85 flash@0{
86 compatible = "jedec,spi-nor";
87 reg = <0x0>;
88 spi-tx-bus-width = <1>;
89 spi-rx-bus-width = <8>;
90 spi-max-frequency = <40000000>;
91 cdns,tshsl-ns = <60>;
92 cdns,tsd2d-ns = <60>;
93 cdns,tchsh-ns = <60>;
94 cdns,tslch-ns = <60>;
95 cdns,read-delay = <0>;
96 #address-cells = <1>;
97 #size-cells = <1>;
98 };
99};