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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk024a26b2002-08-21 21:35:08 +00002/*
3 * (C) Copyright 2002
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk024a26b2002-08-21 21:35:08 +00005 */
6
Wolfgang Denk53677ef2008-05-20 16:00:29 +02007#include <linux/types.h> /* for ulong typedef */
wdenk024a26b2002-08-21 21:35:08 +00008
9#ifndef _FPGA_H_
10#define _FPGA_H_
11
wdenk024a26b2002-08-21 21:35:08 +000012/* fpga_xxxx function return value definitions */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020013#define FPGA_SUCCESS 0
Alexander Dahl5a4675a2019-06-28 14:41:24 +020014#define FPGA_FAIL 1
wdenk024a26b2002-08-21 21:35:08 +000015
16/* device numbers must be non-negative */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020017#define FPGA_INVALID_DEVICE -1
wdenk024a26b2002-08-21 21:35:08 +000018
Adrian Fiergolskib524f8f2022-07-22 17:16:14 +030019#define FPGA_ENC_DEV_KEY 0
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053020#define FPGA_ENC_USR_KEY 1
21#define FPGA_NO_ENC_OR_NO_AUTH 2
22
wdenk024a26b2002-08-21 21:35:08 +000023/* root data type defintions */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020024typedef enum { /* typedef fpga_type */
25 fpga_min_type, /* range check value */
26 fpga_xilinx, /* Xilinx Family) */
27 fpga_altera, /* unimplemented */
Stefano Babic3b8ac462010-06-29 11:47:48 +020028 fpga_lattice, /* Lattice family */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020029 fpga_undefined /* invalid range check value */
30} fpga_type; /* end, typedef fpga_type */
wdenk024a26b2002-08-21 21:35:08 +000031
Wolfgang Denk53677ef2008-05-20 16:00:29 +020032typedef struct { /* typedef fpga_desc */
33 fpga_type devtype; /* switch value to select sub-functions */
34 void *devdesc; /* real device descriptor */
35} fpga_desc; /* end, typedef fpga_desc */
wdenk024a26b2002-08-21 21:35:08 +000036
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053037typedef struct { /* typedef fpga_desc */
38 unsigned int blocksize;
39 char *interface;
40 char *dev_part;
Tien Fong Chee3003c442019-02-15 15:57:07 +080041 const char *filename;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053042 int fstype;
43} fpga_fs_info;
wdenk024a26b2002-08-21 21:35:08 +000044
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053045struct fpga_secure_info {
46 u8 *userkey_addr;
47 u8 authflag;
48 u8 encflag;
49};
50
Michal Simek7a78bd22014-05-02 14:09:30 +020051typedef enum {
52 BIT_FULL = 0,
Michal Simek67193862014-05-02 13:43:39 +020053 BIT_PARTIAL,
Siva Durga Prasad Paladuguddbcf8f2015-12-09 18:46:42 +053054 BIT_NONE = 0xFF,
Michal Simek7a78bd22014-05-02 14:09:30 +020055} bitstream_type;
56
wdenk024a26b2002-08-21 21:35:08 +000057/* root function definitions */
Michal Simek65835052015-01-14 09:59:00 +010058void fpga_init(void);
59int fpga_add(fpga_type devtype, void *desc);
60int fpga_count(void);
Michal Simekebd322d2015-01-13 16:09:53 +010061const fpga_desc *const fpga_get_desc(int devnum);
Goldschmidt Simon8b93a922017-11-10 14:17:41 +000062int fpga_is_partial_data(int devnum, size_t img_len);
Chanho Park55e28102023-08-31 16:52:47 +090063#if CONFIG_IS_ENABLED(FPGA)
Michal Simek65835052015-01-14 09:59:00 +010064int fpga_load(int devnum, const void *buf, size_t bsize,
Oleksandr Suvorov282eed52022-07-22 17:16:07 +030065 bitstream_type bstype, int flags);
Chanho Park55e28102023-08-31 16:52:47 +090066#else
67static inline int fpga_load(int devnum, const void *buf, size_t bsize,
68 bitstream_type bstype, int flags)
69{
70 return FPGA_FAIL;
71}
72#endif
Michal Simek65835052015-01-14 09:59:00 +010073int fpga_fsload(int devnum, const void *buf, size_t size,
74 fpga_fs_info *fpga_fsinfo);
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053075int fpga_loads(int devnum, const void *buf, size_t size,
76 struct fpga_secure_info *fpga_sec_info);
Michal Simek65835052015-01-14 09:59:00 +010077int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
78 bitstream_type bstype);
79int fpga_dump(int devnum, const void *buf, size_t bsize);
80int fpga_info(int devnum);
81const fpga_desc *const fpga_validate(int devnum, const void *buf,
82 size_t bsize, char *fn);
Oleksandr Suvorov2c605142022-07-22 17:16:08 +030083int fpga_compatible2flag(int devnum, const char *compatible);
wdenk024a26b2002-08-21 21:35:08 +000084
85#endif /* _FPGA_H_ */