| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com |
| 4 | * |
| Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 8 | #include <asm-offsets.h> |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 9 | #include <ppc_asm.tmpl> |
| Peter Tyser | 61f2b38 | 2010-04-12 22:28:07 -0500 | [diff] [blame] | 10 | #include <asm/mmu.h> |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 11 | #include <config.h> |
| 12 | |
| 13 | /* |
| 14 | * TLB TABLE |
| 15 | * |
| 16 | * This table is used by the cpu boot code to setup the initial tlb |
| 17 | * entries. Rather than make broad assumptions in the cpu source tree, |
| 18 | * this table lets each board set things up however they like. |
| 19 | * |
| 20 | * Pointer to the table is returned in r1 |
| 21 | */ |
| 22 | .section .bootpg,"ax" |
| 23 | .globl tlbtab |
| 24 | |
| 25 | tlbtab: |
| 26 | tlbtab_start |
| 27 | |
| 28 | /* |
| 29 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the |
| 30 | * speed up boot process. It is patched after relocation to enable SA_I |
| 31 | */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 32 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 33 | |
| Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 34 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 35 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 36 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 37 | #endif |
| 38 | |
| 39 | /* TLB-entry for PCI Memory */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 40 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) |
| 41 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) |
| 42 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) |
| 43 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 44 | |
| 45 | /* TLB-entry for PCI IO */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 46 | tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG ) |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 47 | |
| 48 | /* TLB-entries for EBC: CPLD, DUMEM, DUIO */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 49 | tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG ) |
| 50 | tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG ) |
| 51 | tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG ) |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 52 | |
| 53 | /* TLB-entry for NAND */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 54 | tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG ) |
| 55 | tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG ) |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 56 | |
| 57 | /* TLB-entry for Internal Registers & OCM */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 58 | tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 59 | |
| 60 | /* TLB-entry PCI registers */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 61 | tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 62 | |
| 63 | /* TLB-entry for peripherals */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 64 | tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) |
| Matthias Fuchs | 15a08bc | 2008-01-17 10:52:30 +0100 | [diff] [blame] | 65 | |
| 66 | tlbtab_end |