blob: 43bb4df4da72384319d6afe3dee9e058ed22d0bc [file] [log] [blame]
Stefan Roese4751e552018-10-08 12:38:01 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
4 *
5 * Based on the Linux driver version which is:
6 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
8 */
9
10#include <common.h>
11#include <dm.h>
12#include <errno.h>
13#include <fdtdec.h>
14#include <malloc.h>
Simon Glasscd93d622020-05-10 11:40:13 -060015#include <linux/bitops.h>
Stefan Roese4751e552018-10-08 12:38:01 +020016#include <linux/io.h>
17#include <asm/io.h>
18#include <asm/gpio.h>
19#include <dm/device-internal.h>
20#include <dt-bindings/gpio/gpio.h>
21
22#define MTK_MAX_BANK 3
23#define MTK_BANK_WIDTH 32
24
25enum mediatek_gpio_reg {
26 GPIO_REG_CTRL = 0,
27 GPIO_REG_POL,
28 GPIO_REG_DATA,
29 GPIO_REG_DSET,
30 GPIO_REG_DCLR,
31 GPIO_REG_REDGE,
32 GPIO_REG_FEDGE,
33 GPIO_REG_HLVL,
34 GPIO_REG_LLVL,
35 GPIO_REG_STAT,
36 GPIO_REG_EDGE,
37};
38
39static void __iomem *mediatek_gpio_membase;
40
Simon Glass8a8d24b2020-12-03 16:55:23 -070041struct mediatek_gpio_plat {
Stefan Roese4751e552018-10-08 12:38:01 +020042 char bank_name[3]; /* Name of bank, e.g. "PA", "PB" etc */
43 int gpio_count;
44 int bank;
45};
46
Simon Glass8a8d24b2020-12-03 16:55:23 -070047static u32 reg_offs(struct mediatek_gpio_plat *plat, int reg)
Stefan Roese4751e552018-10-08 12:38:01 +020048{
49 return (reg * 0x10) + (plat->bank * 0x4);
50}
51
52static int mediatek_gpio_get_value(struct udevice *dev, unsigned int offset)
53{
Simon Glass8a8d24b2020-12-03 16:55:23 -070054 struct mediatek_gpio_plat *plat = dev_get_plat(dev);
Stefan Roese4751e552018-10-08 12:38:01 +020055
56 return !!(ioread32(mediatek_gpio_membase +
57 reg_offs(plat, GPIO_REG_DATA)) & BIT(offset));
58}
59
60static int mediatek_gpio_set_value(struct udevice *dev, unsigned int offset,
61 int value)
62{
Simon Glass8a8d24b2020-12-03 16:55:23 -070063 struct mediatek_gpio_plat *plat = dev_get_plat(dev);
Stefan Roese4751e552018-10-08 12:38:01 +020064
65 iowrite32(BIT(offset), mediatek_gpio_membase +
66 reg_offs(plat, value ? GPIO_REG_DSET : GPIO_REG_DCLR));
67
68 return 0;
69}
70
71static int mediatek_gpio_direction_input(struct udevice *dev, unsigned int offset)
72{
Simon Glass8a8d24b2020-12-03 16:55:23 -070073 struct mediatek_gpio_plat *plat = dev_get_plat(dev);
Stefan Roese4751e552018-10-08 12:38:01 +020074
75 clrbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL),
76 BIT(offset));
77
78 return 0;
79}
80
81static int mediatek_gpio_direction_output(struct udevice *dev, unsigned int offset,
82 int value)
83{
Simon Glass8a8d24b2020-12-03 16:55:23 -070084 struct mediatek_gpio_plat *plat = dev_get_plat(dev);
Stefan Roese4751e552018-10-08 12:38:01 +020085
86 setbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL),
87 BIT(offset));
88 mediatek_gpio_set_value(dev, offset, value);
89
90 return 0;
91}
92
93static int mediatek_gpio_get_function(struct udevice *dev, unsigned int offset)
94{
Simon Glass8a8d24b2020-12-03 16:55:23 -070095 struct mediatek_gpio_plat *plat = dev_get_plat(dev);
Stefan Roese4751e552018-10-08 12:38:01 +020096 u32 t;
97
98 t = ioread32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL));
99 if (t & BIT(offset))
100 return GPIOF_OUTPUT;
101
102 return GPIOF_INPUT;
103}
104
105static const struct dm_gpio_ops gpio_mediatek_ops = {
106 .direction_input = mediatek_gpio_direction_input,
107 .direction_output = mediatek_gpio_direction_output,
108 .get_value = mediatek_gpio_get_value,
109 .set_value = mediatek_gpio_set_value,
110 .get_function = mediatek_gpio_get_function,
111};
112
113static int gpio_mediatek_probe(struct udevice *dev)
114{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700115 struct mediatek_gpio_plat *plat = dev_get_plat(dev);
Stefan Roese4751e552018-10-08 12:38:01 +0200116 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
117
118 /* Tell the uclass how many GPIOs we have */
119 if (plat) {
120 uc_priv->gpio_count = plat->gpio_count;
121 uc_priv->bank_name = plat->bank_name;
122 }
123
124 return 0;
125}
126
127/**
128 * We have a top-level GPIO device with no actual GPIOs. It has a child
129 * device for each Mediatek bank.
130 */
131static int gpio_mediatek_bind(struct udevice *parent)
132{
Simon Glass0fd3d912020-12-22 19:30:28 -0700133 struct mediatek_gpio_plat *plat = dev_get_plat(parent);
Stefan Roese4751e552018-10-08 12:38:01 +0200134 ofnode node;
135 int bank = 0;
136 int ret;
137
138 /* If this is a child device, there is nothing to do here */
139 if (plat)
140 return 0;
141
142 mediatek_gpio_membase = dev_remap_addr(parent);
143 if (!mediatek_gpio_membase)
144 return -EINVAL;
145
146 for (node = dev_read_first_subnode(parent); ofnode_valid(node);
147 node = dev_read_next_subnode(node)) {
Simon Glass8a8d24b2020-12-03 16:55:23 -0700148 struct mediatek_gpio_plat *plat;
Stefan Roese4751e552018-10-08 12:38:01 +0200149 struct udevice *dev;
150
151 plat = calloc(1, sizeof(*plat));
152 if (!plat)
153 return -ENOMEM;
154 plat->bank_name[0] = 'P';
155 plat->bank_name[1] = 'A' + bank;
156 plat->bank_name[2] = '\0';
157 plat->gpio_count = MTK_BANK_WIDTH;
158 plat->bank = bank;
159
Simon Glassa2703ce2020-11-28 17:50:03 -0700160 ret = device_bind(parent, parent->driver, plat->bank_name, plat,
Simon Glass20da4e02020-11-28 17:50:04 -0700161 node, &dev);
Stefan Roese4751e552018-10-08 12:38:01 +0200162 if (ret)
163 return ret;
164
Stefan Roese4751e552018-10-08 12:38:01 +0200165 bank++;
166 }
167
168 return 0;
169}
170
171static const struct udevice_id mediatek_gpio_ids[] = {
172 { .compatible = "mtk,mt7621-gpio" },
173 { }
174};
175
176U_BOOT_DRIVER(gpio_mediatek) = {
177 .name = "gpio_mediatek",
178 .id = UCLASS_GPIO,
179 .ops = &gpio_mediatek_ops,
180 .of_match = mediatek_gpio_ids,
181 .bind = gpio_mediatek_bind,
182 .probe = gpio_mediatek_probe,
183};