| Tom Rini | efb5dab7 | 2021-08-21 13:50:17 -0400 | [diff] [blame] | 1 | choice |
| 2 | prompt "Method to determine DDR clock frequency" |
| 3 | default STATIC_DDR_CLK_FREQ |
| 4 | depends on ARCH_P1010 || ARCH_P1020 || ARCH_P2020 || ARCH_T1024 \ |
| 5 | || ARCH_T1042 || ARCH_T2080 || ARCH_T4240 || ARCH_LS1021A \ |
| 6 | || FSL_LSCH2 || FSL_LSCH3 || TARGET_KMCENT2 |
| 7 | help |
| 8 | The DDR clock frequency can either be defined statically now at |
| 9 | build time, or can be determined at run-time via the |
| 10 | get_board_ddr_clk function. |
| 11 | |
| 12 | config DYNAMIC_DDR_CLK_FREQ |
| 13 | bool "Run-time DDR clock frequency" |
| 14 | |
| 15 | config STATIC_DDR_CLK_FREQ |
| 16 | bool "Build-time static DDR clock frequency" |
| 17 | |
| 18 | endchoice |
| 19 | |
| 20 | config DDR_CLK_FREQ |
| 21 | int "DDR clock frequency in Hz" |
| 22 | depends on STATIC_DDR_CLK_FREQ |
| 23 | default 100000000 |
| 24 | help |
| 25 | The DDR clock frequency, specified in Hz. |
| 26 | |
| Tom Rini | 222d22a | 2021-08-21 13:50:16 -0400 | [diff] [blame] | 27 | config DDR_SPD |
| 28 | bool "JEDEC Serial Presence Detect (SPD) support" |
| 29 | help |
| 30 | For memory controllers that can utilize it, add enable support for |
| 31 | using the JEDEC SDP standard. |
| 32 | |
| Tom Rini | bca4509 | 2022-06-15 12:03:54 -0400 | [diff] [blame^] | 33 | config SYS_SPD_BUS_NUM |
| 34 | int "I2C bus number for DDR SPD" |
| 35 | depends on DDR_SPD || SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY |
| 36 | default 0 |
| 37 | |
| Ley Foon Tan | 707cd01 | 2017-04-05 17:32:51 +0800 | [diff] [blame] | 38 | source "drivers/ddr/altera/Kconfig" |
| Peng Fan | e3963c0 | 2018-11-20 10:19:57 +0000 | [diff] [blame] | 39 | source "drivers/ddr/imx/Kconfig" |