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Heiko Schocherca43ba12007-01-11 15:44:44 +01001/*------------------------------------------------------------------------------+
2 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +01003 * This souce code has been made available to you by EuroDesign
4 * (www.eurodsn.de). It's based on the original IBM source code, so
5 * this follows:
Heiko Schocherca43ba12007-01-11 15:44:44 +01006 *
Josh Boyer31773492009-08-07 13:53:20 -04007 * This source code is dual-licensed. You may use it under the terms of the
8 * GNU General Public License version 2, or under the license below.
9 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +010010 * This source code has been made available to you by IBM on an AS-IS
11 * basis. Anyone receiving this source is licensed under IBM
12 * copyrights to use it in any way he or she deems fit, including
13 * copying it, modifying it, compiling it, and redistributing it either
14 * with or without modifications. No license under IBM patents or
15 * patent applications is to be implied by the copyright license.
Heiko Schocherca43ba12007-01-11 15:44:44 +010016 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +010017 * Any user of this software should understand that IBM cannot provide
18 * technical support for this software and will not be responsible for
19 * any consequences resulting from the use of this software.
Heiko Schocherca43ba12007-01-11 15:44:44 +010020 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +010021 * Any person who transfers this source code or any derivative work
22 * must include the IBM copyright notice, this paragraph, and the
23 * preceding two paragraphs in the transferred software.
Heiko Schocherca43ba12007-01-11 15:44:44 +010024 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +010025 * COPYRIGHT I B M CORPORATION 1995
26 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
Heiko Schocherca43ba12007-01-11 15:44:44 +010027 *------------------------------------------------------------------------------- */
28
29#include <config.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020030#include <asm/ppc4xx.h>
Heiko Schocherca43ba12007-01-11 15:44:44 +010031
32#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
33
34#include <ppc_asm.tmpl>
35#include <ppc_defs.h>
36
37#include <asm/cache.h>
38#include <asm/mmu.h>
39
40/**
41 * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
42 *
43 * IMPORTANT: For pass1 this code must run from cache since you can not
44 * reliably change a peripheral banks timing register (pbxap) while running
45 * code from that bank. For ex., since we are running from ROM on bank 0, we
46 * can NOT execute the code that modifies bank 0 timings from ROM, so
47 * we run it from cache.
48 *
49 * Bank 0 - Boot-Flash
50 * Bank 1 - NAND-Flash
51 * Bank 2 - ISA bus
52 * Bank 3 - Second Flash
53 * Bank 4 - USB controller
54 */
55 .globl ext_bus_cntlr_init
56ext_bus_cntlr_init:
57/*
58 * We need the current boot up configuration to set correct
59 * timings into internal flash and external flash
60 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020061 mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
Wolfgang Denkf11033e2007-01-15 13:41:04 +010062 0 0 -> 8 bit external ROM
63 0 1 -> 16 bit internal ROM */
Heiko Schocherca43ba12007-01-11 15:44:44 +010064 addi r4,0,2
65 srw r24,r24,r4 /* shift right r24 two positions */
66 andi. r24,r24,0x06000
Wolfgang Denkf11033e2007-01-15 13:41:04 +010067/*
Heiko Schocherca43ba12007-01-11 15:44:44 +010068 * All calculations are based on 33MHz EBC clock.
69 *
70 * First, create a "very slow" timing (~250ns) with burst mode enabled
71 * This is need for the external flash access
72 */
73 lis r25,0x0800
Jeroen Hofstee3fd1e852013-01-08 13:35:53 +000074 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
75 ori r25,r25,0x0280
Heiko Schocherca43ba12007-01-11 15:44:44 +010076/*
77 * Second, create a fast timing:
78 * 90ns first cycle - 3 clock access
79 * and 90ns burst cycle, plus 1 clock after the last access
80 * This is used for the internal access
81 */
82 lis r26,0x8900
Jeroen Hofstee3fd1e852013-01-08 13:35:53 +000083 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
84 ori r26,r26,0x0280
Heiko Schocherca43ba12007-01-11 15:44:44 +010085/*
86 * We can't change settings on CS# if we currently use them.
87 * -> load a few instructions into cache and run this code from cache
88 */
89 mflr r4 /* save link register */
90 bl ..getAddr
91..getAddr:
92 mflr r3 /* get address of ..getAddr */
93 mtlr r4 /* restore link register */
94 addi r4,0,14 /* set ctr to 10; used to prefetch */
95 mtctr r4 /* 10 cache lines to fit this function
96 in cache (gives us 8x10=80 instructions) */
97..ebcloop:
98 icbt r0,r3 /* prefetch cache line for addr in r3 */
99 addi r3,r3,32 /* move to next cache line */
100 bdnz ..ebcloop /* continue for 10 cache lines */
101/*
102 * Delay to ensure all accesses to ROM are complete before changing
103 * bank 0 timings. 200usec should be enough.
104 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
105 */
106 lis r3,0x0
107 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
108 mtctr r3
109..spinlp:
110 bdnz ..spinlp /* spin loop */
111
112/*-----------------------------------------------------------------------
113 * Memory Bank 0 (BOOT-ROM) initialization
114 * 0xFFEF00000....0xFFFFFFF
115 * We only have to change the timing. Mapping is ok by boot-strapping
116 *----------------------------------------------------------------------- */
117
Stefan Roesed1c3b272009-09-09 16:25:29 +0200118 li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */
119 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100120
121 mr r4,r26 /* assume internal fast flash is boot flash */
122 cmpwi r24,0x2000 /* assumption true? ... */
123 beq 1f /* ...yes! */
124 mr r4,r25 /* ...no, use the slow variant */
125 mr r25,r26 /* use this for the other flash */
1261:
Stefan Roesed1c3b272009-09-09 16:25:29 +0200127 mtdcr EBC0_CFGDATA,r4 /* change timing now */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100128
Stefan Roesed1c3b272009-09-09 16:25:29 +0200129 li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */
130 mtdcr EBC0_CFGADDR,r4
131 mfdcr r4,EBC0_CFGDATA
Heiko Schocherca43ba12007-01-11 15:44:44 +0100132 lis r3,0x0001
133 ori r3,r3,0x8000 /* allow reads and writes */
134 or r4,r4,r3
Stefan Roesed1c3b272009-09-09 16:25:29 +0200135 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100136
137/*-----------------------------------------------------------------------
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100138 * Memory Bank 3 (Second-Flash) initialization
Heiko Schocherca43ba12007-01-11 15:44:44 +0100139 * 0xF0000000...0xF01FFFFF -> 2MB
140 *----------------------------------------------------------------------- */
141
Stefan Roesed1c3b272009-09-09 16:25:29 +0200142 li r4,PB3AP /* Peripheral Bank 1 Access Parameter */
143 mtdcr EBC0_CFGADDR,r4
144 mtdcr EBC0_CFGDATA,r2 /* change timing */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100145
Stefan Roesed1c3b272009-09-09 16:25:29 +0200146 li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */
147 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100148
149 lis r4,0xF003
150 ori r4,r4,0x8000
151/*
152 * Consider boot configuration
153 */
154 xori r24,r24,0x2000 /* invert current bus width */
155 or r4,r4,r24
Stefan Roesed1c3b272009-09-09 16:25:29 +0200156 mtdcr EBC0_CFGDATA,r4
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100157
Heiko Schocherca43ba12007-01-11 15:44:44 +0100158/*-----------------------------------------------------------------------
159 * Memory Bank 1 (NAND-Flash) initialization
160 * 0x77D00000...0x77DFFFFF -> 1MB
161 * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
162 * - the setup time is 0ns
163 * - the hold time is 15ns
164 * ->
165 * - TWT = 0
166 * - CSN = 0
167 * - OEN = 0
168 * - WBN = 0
169 * - WBF = 0
170 * - TH = 1
171 * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
172 *----------------------------------------------------------------------- */
173
Stefan Roesed1c3b272009-09-09 16:25:29 +0200174 li r4,PB1AP /* Peripheral Bank 1 Access Parameter */
175 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100176
177 lis r4,0x0000
178 ori r4,r4,0x0200
Stefan Roesed1c3b272009-09-09 16:25:29 +0200179 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100180
Stefan Roesed1c3b272009-09-09 16:25:29 +0200181 li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */
182 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100183
184 lis r4,0x77D1
185 ori r4,r4,0x8000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200186 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100187
188
189/* USB init (without acceleration) */
190#ifndef CONFIG_ISP1161_PRESENT
Stefan Roesed1c3b272009-09-09 16:25:29 +0200191 li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
192 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100193 lis r4,0x0180
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100194 ori r4,r4,0x5940
Stefan Roesed1c3b272009-09-09 16:25:29 +0200195 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100196#endif
197
198/*-----------------------------------------------------------------------
199 * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
200 * 0x78000000...0x7BFFFFFF -> 64 MB
201 * Wir arbeiten bei 33 MHz -> 30ns
202 *-----------------------------------------------------------------------
203
204 A7 (ppc notation) or A24 (standard notation) decides about
205 the type of access:
206 A7/A24=0 -> memory cycle
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100207 A7/ /A24=1 -> I/O cycle
Heiko Schocherca43ba12007-01-11 15:44:44 +0100208*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200209 li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */
210 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100211/*
212 We emulate an ISA access
213
214 1. Address active
215 2. wait 0 EBC clocks -> CSN=0
216 3. set CS#
217 4. wait 0 EBC clock -> OEN/WBN=0
218 5. set OE#/WE#
219 6. wait 4 clocks (ca. 90ns) and for Ready signal
220 7. hold for 4 clocks -> TH=4
221*/
222
223#if 1
224/* faster access to isa-bus */
225 lis r4,0x0180
226 ori r4,r4,0x5940
227#else
228 lis r4,0x0100
229 ori r4,r4,0x0340
230#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +0200231 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100232
233#ifdef IDE_USES_ISA_EMULATION
Stefan Roesed1c3b272009-09-09 16:25:29 +0200234 li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */
235 mtdcr EBC0_CFGADDR,r25
236 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100237#endif
238
Stefan Roesed1c3b272009-09-09 16:25:29 +0200239 li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */
240 mtdcr EBC0_CFGADDR,r25
241 mtdcr EBC0_CFGDATA,r4
242 li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */
243 mtdcr EBC0_CFGADDR,r25
244 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100245
Stefan Roesed1c3b272009-09-09 16:25:29 +0200246 li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */
247 mtdcr EBC0_CFGADDR,r25
Heiko Schocherca43ba12007-01-11 15:44:44 +0100248
249 lis r4,0x780B
250 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200251 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100252/*
253 * the other areas are only 1MiB in size
254 */
255 lis r4,0x7401
256 ori r4,r4,0xA000
257
Stefan Roesed1c3b272009-09-09 16:25:29 +0200258 li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */
259 mtdcr EBC0_CFGADDR,r25
Heiko Schocherca43ba12007-01-11 15:44:44 +0100260 lis r4,0x7401
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100261 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200262 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100263
Stefan Roesed1c3b272009-09-09 16:25:29 +0200264 li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */
265 mtdcr EBC0_CFGADDR,r25
Heiko Schocherca43ba12007-01-11 15:44:44 +0100266 lis r4,0x7411
267 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200268 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100269
270#ifndef CONFIG_ISP1161_PRESENT
Stefan Roesed1c3b272009-09-09 16:25:29 +0200271 li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */
272 mtdcr EBC0_CFGADDR,r25
Heiko Schocherca43ba12007-01-11 15:44:44 +0100273 lis r4,0x7421
274 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200275 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100276#endif
277#ifdef IDE_USES_ISA_EMULATION
Stefan Roesed1c3b272009-09-09 16:25:29 +0200278 li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */
279 mtdcr EBC0_CFGADDR,r25
Heiko Schocherca43ba12007-01-11 15:44:44 +0100280 lis r4,0x0000
281 ori r4,r4,0x0000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200282 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100283#endif
284
285/*-----------------------------------------------------------------------
286 * Memory bank 4: USB controller Philips ISP6111
287 * 0x77C00000 ... 0x77CFFFFF
288 *
289 * The chip is connected to:
290 * - CPU CS#4
291 * - CPU IRQ#2
292 * - CPU DMA 3
293 *
294 * Timing:
295 * - command to first data: 300ns. Software must ensure this timing!
296 * - Write pulse: 26ns
297 * - Read pulse: 33ns
298 * - read cycle time: 150ns
299 * - write cycle time: 140ns
300 *
301 * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
302 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100303 * |- 300ns --|
304 * |---- 420ns ---|---- 420ns ---| cycle
Heiko Schocherca43ba12007-01-11 15:44:44 +0100305 * CS ############:###____#######:###____#######
306 * OE ############:####___#######:####___#######
307 * WE ############:####__########:####__########
308 *
309 * ----> 2 clocks RD/WR pulses: 60ns
310 * ----> CSN: 3 clock, 90ns
311 * ----> OEN: 1 clocks (read cycle)
312 * ----> WBN: 1 clocks (write cycle)
313 * ----> WBE: 2 clocks
314 * ----> TH: 7 clock, 210ns
315 * ----> TWT: 7 clocks
316 *----------------------------------------------------------------------- */
317
318#ifdef CONFIG_ISP1161_PRESENT
319
Stefan Roesed1c3b272009-09-09 16:25:29 +0200320 li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
321 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100322
323 lis r4,0x030D
324 ori r4,r4,0x5E80
Stefan Roesed1c3b272009-09-09 16:25:29 +0200325 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100326
Stefan Roesed1c3b272009-09-09 16:25:29 +0200327 li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */
328 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100329
330 lis r4,0x77C1
331 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200332 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100333
334#endif
335
336#ifndef IDE_USES_ISA_EMULATION
337
338/*-----------------------------------------------------------------------
339 * Memory Bank 5 used for IDE access
340 *
341 * Timings for IDE Interface
342 *
343 * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
344 * 70 165 30 PIO-Mode 0, [ns]
345 * 3 6 1 [Cycles] ----> AP=0x040C0200
346 * 50 125 20 PIO-Mode 1, [ns]
347 * 2 5 1 [Cycles] ----> AP=0x03080200
348 * 30 100 15 PIO-Mode 2, [ns]
349 * 1 4 1 [Cycles] ----> AP=0x02040200
350 * 30 80 10 PIO-Mode 3, [ns]
351 * 1 3 1 [Cycles] ----> AP=0x01840200
352 * 25 70 10 PIO-Mode 4, [ns]
353 * 1 3 1 [Cycles] ----> AP=0x01840200
354 *
355 *----------------------------------------------------------------------- */
356
Stefan Roesed1c3b272009-09-09 16:25:29 +0200357 li r4,PB5AP
358 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100359 lis r4,0x040C
360 ori r4,r4,0x0200
Stefan Roesed1c3b272009-09-09 16:25:29 +0200361 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100362
Stefan Roesed1c3b272009-09-09 16:25:29 +0200363 li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */
364 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100365
366 lis r4,0x7A01
367 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200368 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100369#endif
370/*
371 * External Peripheral Control Register
372 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200373 li r4,EBC0_CFG
374 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100375
376 lis r4,0xB84E
377 ori r4,r4,0xF000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200378 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100379/*
380 * drive POST code
381 */
382 lis r4,0x7900
383 ori r4,r4,0x0080
384 li r3,0x0001
385 stb r3,0(r4) /* 01 -> external bus controller is initialized */
386 nop /* pass2 DCR errata #8 */
387 blr