| Marek Vasut | bd39050 | 2017-07-21 23:15:21 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * include/configs/ulcb.h |
| 3 | * This file is ULCB board configuration. |
| 4 | * |
| 5 | * Copyright (C) 2017 Renesas Electronics Corporation |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #ifndef __ULCB_H |
| 11 | #define __ULCB_H |
| 12 | |
| 13 | #undef DEBUG |
| 14 | |
| 15 | #define CONFIG_RCAR_BOARD_STRING "ULCB" |
| 16 | |
| 17 | #include "rcar-gen3-common.h" |
| 18 | |
| 19 | /* M3 ULCB has 2 banks, each with 1 GiB of RAM */ |
| 20 | #if defined(CONFIG_R8A7796) |
| 21 | #undef PHYS_SDRAM_1_SIZE |
| 22 | #undef PHYS_SDRAM_2_SIZE |
| 23 | #define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) |
| 24 | #define PHYS_SDRAM_2_SIZE 0x40000000u |
| 25 | #endif |
| 26 | |
| 27 | /* SCIF */ |
| 28 | #define CONFIG_SCIF_CONSOLE |
| 29 | #define CONFIG_CONS_SCIF2 |
| 30 | #define CONFIG_CONS_INDEX 2 |
| 31 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ |
| 32 | |
| 33 | /* [A] Hyper Flash */ |
| 34 | /* use to RPC(SPI Multi I/O Bus Controller) */ |
| 35 | |
| 36 | /* Ethernet RAVB */ |
| 37 | #define CONFIG_NET_MULTI |
| 38 | #define CONFIG_PHY_MICREL |
| 39 | #define CONFIG_BITBANGMII |
| 40 | #define CONFIG_BITBANGMII_MULTI |
| 41 | |
| 42 | /* Board Clock */ |
| 43 | /* XTAL_CLK : 33.33MHz */ |
| 44 | #define RCAR_XTAL_CLK 33333333u |
| 45 | #define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK |
| 46 | /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ |
| 47 | /* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ |
| 48 | #define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) |
| 49 | #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) |
| 50 | #define CONFIG_S3D2_CLK_FREQ (266666666u/2) |
| 51 | #define CONFIG_S3D4_CLK_FREQ (266666666u/4) |
| 52 | |
| 53 | /* Generic Timer Definitions (use in assembler source) */ |
| 54 | #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ |
| 55 | |
| 56 | /* Generic Interrupt Controller Definitions */ |
| 57 | #define CONFIG_GICV2 |
| 58 | #define GICD_BASE 0xF1010000 |
| 59 | #define GICC_BASE 0xF1020000 |
| 60 | |
| 61 | /* CPLD SPI */ |
| 62 | #define CONFIG_CMD_SPI |
| 63 | #define CONFIG_SOFT_SPI |
| 64 | #define SPI_DELAY udelay(0) |
| 65 | #define SPI_SDA(val) ulcb_softspi_sda(val) |
| 66 | #define SPI_SCL(val) ulcb_softspi_scl(val) |
| 67 | #define SPI_READ ulcb_softspi_read() |
| 68 | #ifndef __ASSEMBLY__ |
| 69 | void ulcb_softspi_sda(int); |
| 70 | void ulcb_softspi_scl(int); |
| 71 | unsigned char ulcb_softspi_read(void); |
| 72 | #endif |
| 73 | |
| 74 | /* i2c */ |
| 75 | #define CONFIG_SYS_I2C |
| 76 | #define CONFIG_SYS_I2C_SH |
| 77 | #define CONFIG_SYS_I2C_SLAVE 0x60 |
| 78 | #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 |
| 79 | #define CONFIG_SYS_I2C_SH_SPEED0 400000 |
| 80 | #define CONFIG_SH_I2C_DATA_HIGH 4 |
| 81 | #define CONFIG_SH_I2C_DATA_LOW 5 |
| 82 | #define CONFIG_SH_I2C_CLOCK 10000000 |
| 83 | |
| 84 | #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 |
| 85 | |
| 86 | /* USB */ |
| 87 | #ifdef CONFIG_R8A7795 |
| 88 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
| 89 | #else |
| 90 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
| 91 | #endif |
| 92 | |
| 93 | /* SDHI */ |
| 94 | #define CONFIG_SH_SDHI_FREQ 200000000 |
| 95 | |
| 96 | /* Environment in eMMC, at the end of 2nd "boot sector" */ |
| 97 | #define CONFIG_ENV_IS_IN_MMC |
| 98 | #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) |
| 99 | #define CONFIG_SYS_MMC_ENV_DEV 1 |
| 100 | #define CONFIG_SYS_MMC_ENV_PART 2 |
| 101 | |
| 102 | /* Module stop status bits */ |
| 103 | /* MFIS, SCIF1 */ |
| 104 | #define CONFIG_SMSTP2_ENA 0x00002040 |
| 105 | /* SCIF2 */ |
| 106 | #define CONFIG_SMSTP3_ENA 0x00000400 |
| 107 | /* INTC-AP, IRQC */ |
| 108 | #define CONFIG_SMSTP4_ENA 0x00000180 |
| 109 | |
| 110 | #endif /* __ULCB_H */ |