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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / bda4dece03675ad30c098a00f20332010ccb5c5d / . / include / configs / XPEDITE5170.h
blob: 242466ae12048dce561b1fa480a25f442ee71c17 [file] [log] [blame]
Peter Tyser5da6f802009-06-30 17:26:01 -0500[diff] [blame]1/*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * xpedite5170 board configuration file
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_MPC86xx 1 /* MPC86xx */
34#define CONFIG_MPC8641 1 /* MPC8641 specific */
35#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
36#define CONFIG_SYS_BOARD_NAME "XPedite5170"
Peter Tyser5da6f802009-06-30 17:26:01 -0500[diff] [blame]37#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
38#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
39#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */
40#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
41#define CONFIG_ALTIVEC 1
42
43#define CONFIG_PCI 1 /* Enable PCI/PCIE */
44#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
45#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
46#define CONFIG_PCIE1 1 /* PCIE controler 1 */
47#define CONFIG_PCIE2 1 /* PCIE controler 2 */
48#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
49#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
50#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
51
52/*
53 * DDR config
54 */
55#define CONFIG_FSL_DDR2
56#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
57#define CONFIG_DDR_SPD
58#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
59#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
60#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
61#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
62#define CONFIG_NUM_DDR_CONTROLLERS 2
63#define CONFIG_DIMM_SLOTS_PER_CTLR 1
64#define CONFIG_CHIP_SELECTS_PER_CTRL 1
65#define CONFIG_DDR_ECC
66#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
67#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
68#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
69#define CONFIG_VERY_BIG_RAM
70#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
71
72/*
73 * virtual address to be used for temporary mappings. There
74 * should be 128k free at this VA.
75 */
76#define CONFIG_SYS_SCRATCH_VA 0xe0000000
77
78#ifndef __ASSEMBLY__
79extern unsigned long get_board_sys_clk(unsigned long dummy);
80#endif
81
82#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
83
84/*
85 * L2CR setup
86 */
87#define CONFIG_SYS_L2
88#define L2_INIT 0
89#define L2_ENABLE (L2CR_L2E)
90
91/*
92 * Base addresses -- Note these are effective addresses where the
93 * actual resources get mapped (not physical addresses)
94 */
95#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
96#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
97#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
98#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
99#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
100#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
101#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
102#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
103
104/*
105 * Diagnostics
106 */
107#define CONFIG_SYS_ALT_MEMTEST
108#define CONFIG_SYS_MEMTEST_START 0x10000000
109#define CONFIG_SYS_MEMTEST_END 0x20000000
110
111/*
112 * Memory map
113 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
114 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
115 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
116 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
117 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
118 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
119 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
120 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
121 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
122 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
123 */
124
125#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3)
126
127/*
128 * NAND flash configuration
129 */
130#define CONFIG_SYS_NAND_BASE 0xef800000
131#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
132#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
133#define CONFIG_SYS_MAX_NAND_DEVICE 2
134#define CONFIG_NAND_ACTL
135#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
136#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
137#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
138#define CONFIG_SYS_NAND_ACTL_DELAY 25
139#define CONFIG_SYS_NAND_QUIET_TEST
140#define CONFIG_JFFS2_NAND
141
142/*
143 * NOR flash configuration
144 */
145#define CONFIG_SYS_FLASH_BASE 0xf8000000
146#define CONFIG_SYS_FLASH_BASE2 0xf0000000
147#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
148#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
149#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
150#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
151#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
152#define CONFIG_FLASH_CFI_DRIVER
153#define CONFIG_SYS_FLASH_CFI
154#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
155#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
156 {0xf7f00000, 0xc0000} }
157#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
158#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
159
160/*
161 * Chip select configuration
162 */
163/* NOR Flash 0 on CS0 */
164#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
165 BR_PS_16 |\
166 BR_V)
167#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
168 OR_GPCM_CSNT |\
169 OR_GPCM_XACS |\
170 OR_GPCM_ACS_DIV2 |\
171 OR_GPCM_SCY_8 |\
172 OR_GPCM_TRLX |\
173 OR_GPCM_EHTR |\
174 OR_GPCM_EAD)
175
176/* NOR Flash 1 on CS1 */
177#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
178 BR_PS_16 |\
179 BR_V)
180#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
181
182/* NAND flash on CS2 */
183#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
184 BR_PS_8 |\
185 BR_V)
186#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
187 OR_GPCM_BCTLD |\
188 OR_GPCM_CSNT |\
189 OR_GPCM_ACS_DIV4 |\
190 OR_GPCM_SCY_4 |\
191 OR_GPCM_TRLX |\
192 OR_GPCM_EHTR)
193
194/* Optional NAND flash on CS3 */
195#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
196 BR_PS_8 |\
197 BR_V)
198#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
199
200/*
201 * Use L1 as initial stack
202 */
203#define CONFIG_SYS_INIT_RAM_LOCK 1
204#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
205#define CONFIG_SYS_INIT_RAM_END 0x00004000
206
207#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
208#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
209#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
210
211#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
212#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
213
214/*
215 * Serial Port
216 */
217#define CONFIG_CONS_INDEX 1
218#define CONFIG_SYS_NS16550
219#define CONFIG_SYS_NS16550_SERIAL
220#define CONFIG_SYS_NS16550_REG_SIZE 1
221#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
222#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
223#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
224#define CONFIG_SYS_BAUDRATE_TABLE \
225 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
226#define CONFIG_BAUDRATE 115200
227#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
228#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
229
230/*
231 * Use the HUSH parser
232 */
233#define CONFIG_SYS_HUSH_PARSER
234#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
235
236/*
237 * Pass open firmware flat tree
238 */
239#define CONFIG_OF_LIBFDT 1
240#define CONFIG_OF_BOARD_SETUP 1
241#define CONFIG_OF_STDOUT_VIA_ALIAS 1
242
243#define CONFIG_SYS_64BIT_VSPRINTF 1
244#define CONFIG_SYS_64BIT_STRTOUL 1
245
246/*
247 * I2C
248 */
249#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
250#define CONFIG_HARD_I2C /* I2C with hardware support */
251#define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */
252#define CONFIG_SYS_I2C_SLAVE 0x7F
253#define CONFIG_SYS_I2C_OFFSET 0x3000
254#define CONFIG_SYS_I2C2_OFFSET 0x3100
255#define CONFIG_I2C_MULTI_BUS
Peter Tyser5da6f802009-06-30 17:26:01 -0500[diff] [blame]256
257/* PEX8518 slave I2C interface */
258#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
259
260/* I2C DS1631 temperature sensor */
261#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
262#define CONFIG_DTT_DS1621
263#define CONFIG_DTT_SENSORS { 0 }
264
265/* I2C EEPROM - AT24C128B */
266#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
267#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
268#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
269#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
270
271/* I2C RTC */
272#define CONFIG_RTC_M41T11 1
273#define CONFIG_SYS_I2C_RTC_ADDR 0x68
274#define CONFIG_SYS_M41T11_BASE_YEAR 2000
275
276/* GPIO/EEPROM/SRAM */
277#define CONFIG_DS4510
278#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
279
280/* GPIO */
281#define CONFIG_PCA953X
282#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
283#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
284#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
285#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
286#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
287
288/*
289 * PU = pulled high, PD = pulled low
290 * I = input, O = output, IO = input/output
291 */
292/* PCA9557 @ 0x18*/
293#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
294#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
295#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
296#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
297#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
298#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
299
300/* PCA9557 @ 0x1c*/
301#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
302#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
303#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
304#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
305#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
306#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
307#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
308#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
309
310/* PCA9557 @ 0x1e*/
311#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
312#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
313#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
314#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
315#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
316#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
317#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
318
319/* PCA9557 @ 0x1f */
320#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
321#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
322#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
323#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
324
325/*
326 * General PCI
327 * Memory space is mapped 1-1, but I/O space must start from 0.
328 */
329/* PCIE1 - PEX8518 */
330#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
331#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
332#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
333#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
334#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
335#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
336
337/* PCIE2 - VPX P1 */
338#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
339#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
340#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
341#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
342#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
343#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
344
345/*
346 * Networking options
347 */
348#define CONFIG_TSEC_ENET /* tsec ethernet support */
349#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
350#define CONFIG_NET_MULTI 1
351#define CONFIG_MII 1 /* MII PHY management */
352#define CONFIG_ETHPRIME "eTSEC1"
353
354#define CONFIG_TSEC1 1
355#define CONFIG_TSEC1_NAME "eTSEC1"
356#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
357#define TSEC1_PHY_ADDR 1
358#define TSEC1_PHYIDX 0
359#define CONFIG_HAS_ETH0
360
361#define CONFIG_TSEC2 1
362#define CONFIG_TSEC2_NAME "eTSEC2"
363#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
364#define TSEC2_PHY_ADDR 2
365#define TSEC2_PHYIDX 0
366#define CONFIG_HAS_ETH1
367
368/*
369 * BAT mappings
370 */
371#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
372#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
373 BATL_PP_RW |\
374 BATL_CACHEINHIBIT |\
375 BATL_GUARDEDSTORAGE)
376#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
377 BATU_BL_1M |\
378 BATU_VS |\
379 BATU_VP)
380#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
381 BATL_PP_RW |\
382 BATL_CACHEINHIBIT)
383#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
384#endif
385
386/*
387 * BAT0 2G Cacheable, non-guarded
388 * 0x0000_0000 2G DDR
389 */
390#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
391#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
392#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
393#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
394
395/*
396 * BAT1 1G Cache-inhibited, guarded
397 * 0x8000_0000 1G PCI-Express 1 Memory
398 */
399#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
400 BATL_PP_RW |\
401 BATL_CACHEINHIBIT |\
402 BATL_GUARDEDSTORAGE)
403#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
404 BATU_BL_1G |\
405 BATU_VS |\
406 BATU_VP)
407#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
408 BATL_PP_RW |\
409 BATL_CACHEINHIBIT)
410#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
411
412/*
413 * BAT2 512M Cache-inhibited, guarded
414 * 0xc000_0000 512M PCI-Express 2 Memory
415 */
416#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
417 BATL_PP_RW |\
418 BATL_CACHEINHIBIT |\
419 BATL_GUARDEDSTORAGE)
420#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
421 BATU_BL_512M |\
422 BATU_VS |\
423 BATU_VP)
424#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
425 BATL_PP_RW |\
426 BATL_CACHEINHIBIT)
427#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
428
429/*
430 * BAT3 1M Cache-inhibited, guarded
431 * 0xe000_0000 1M CCSR
432 */
433#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
434 BATL_PP_RW |\
435 BATL_CACHEINHIBIT |\
436 BATL_GUARDEDSTORAGE)
437#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
438 BATU_BL_1M |\
439 BATU_VS |\
440 BATU_VP)
441#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
442 BATL_PP_RW |\
443 BATL_CACHEINHIBIT)
444#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
445
446/*
447 * BAT4 32M Cache-inhibited, guarded
448 * 0xe200_0000 16M PCI-Express 1 I/O
449 * 0xe300_0000 16M PCI-Express 2 I/0
450 */
451#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
452 BATL_PP_RW |\
453 BATL_CACHEINHIBIT |\
454 BATL_GUARDEDSTORAGE)
455#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
456 BATU_BL_32M |\
457 BATU_VS |\
458 BATU_VP)
459#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
460 BATL_PP_RW |\
461 BATL_CACHEINHIBIT)
462#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
463
464/*
465 * BAT5 128K Cacheable, non-guarded
466 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
467 */
468#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
469 BATL_PP_RW |\
470 BATL_MEMCOHERENCE)
471#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
472 BATU_BL_128K |\
473 BATU_VS |\
474 BATU_VP)
475#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
476#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
477
478/*
479 * BAT6 256M Cache-inhibited, guarded
480 * 0xf000_0000 256M FLASH
481 */
482#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
483 BATL_PP_RW |\
484 BATL_CACHEINHIBIT |\
485 BATL_GUARDEDSTORAGE)
486#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
487 BATU_BL_256M |\
488 BATU_VS |\
489 BATU_VP)
490#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
491 BATL_PP_RW |\
492 BATL_MEMCOHERENCE)
493#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
494
495/* Map the last 1M of flash where we're running from reset */
496#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
497 BATL_PP_RW |\
498 BATL_CACHEINHIBIT |\
499 BATL_GUARDEDSTORAGE)
500#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE |\
501 BATU_BL_1M |\
502 BATU_VS |\
503 BATU_VP)
504#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
505 BATL_PP_RW |\
506 BATL_MEMCOHERENCE)
507#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
508
509/*
510 * BAT7 64M Cache-inhibited, guarded
511 * 0xe800_0000 64K NAND FLASH
512 * 0xe804_0000 128K DUART Registers
513 */
514#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
515 BATL_PP_RW |\
516 BATL_CACHEINHIBIT |\
517 BATL_GUARDEDSTORAGE)
518#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
519 BATU_BL_512K |\
520 BATU_VS |\
521 BATU_VP)
522#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
523 BATL_PP_RW |\
524 BATL_CACHEINHIBIT)
525#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
526
527/*
528 * Command configuration.
529 */
530#include <config_cmd_default.h>
531
532#define CONFIG_CMD_ASKENV
533#define CONFIG_CMD_DATE
534#define CONFIG_CMD_DHCP
535#define CONFIG_CMD_DS4510
536#define CONFIG_CMD_DS4510_INFO
537#define CONFIG_CMD_DTT
538#define CONFIG_CMD_EEPROM
539#define CONFIG_CMD_ELF
540#define CONFIG_CMD_SAVEENV
541#define CONFIG_CMD_FLASH
542#define CONFIG_CMD_I2C
543#define CONFIG_CMD_IRQ
544#define CONFIG_CMD_JFFS2
545#define CONFIG_CMD_MII
546#define CONFIG_CMD_NAND
547#define CONFIG_CMD_NET
548#define CONFIG_CMD_PCA953X
549#define CONFIG_CMD_PCA953X_INFO
550#define CONFIG_CMD_PCI
551#define CONFIG_CMD_PING
552#define CONFIG_CMD_REGINFO
553#define CONFIG_CMD_SNTP
554
555/*
556 * Miscellaneous configurable options
557 */
558#define CONFIG_SYS_LONGHELP /* undef to save memory */
559#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
560#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
561#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
562#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
563#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
564#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
565#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
566#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
567#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
568#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
569#define CONFIG_PANIC_HANG /* do not reset board on panic */
570#define CONFIG_PREBOOT /* enable preboot variable */
571#define CONFIG_FIT 1
572#define CONFIG_FIT_VERBOSE 1
573#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
574
575/*
576 * For booting Linux, the board info and command line data
577 * have to be in the first 16 MB of memory, since this is
578 * the maximum mapped by the Linux kernel during initialization.
579 */
580#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Peter Tyser39121c02009-07-21 13:51:07 -0500[diff] [blame]581#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Peter Tyser5da6f802009-06-30 17:26:01 -0500[diff] [blame]582
583/*
584 * Boot Flags
585 */
586#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
587#define BOOTFLAG_WARM 0x02 /* Software reboot */
588
589/*
590 * Environment Configuration
591 */
592#define CONFIG_ENV_IS_IN_FLASH 1
593#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
594#define CONFIG_ENV_SIZE 0x8000
595#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
596
597/*
598 * Flash memory map:
599 * fffc0000 - ffffffff Pri FDT (256KB)
600 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
601 * fff00000 - fff7ffff Pri U-Boot (512 KB)
602 * fef00000 - ffefffff Pri OS image (16MB)
603 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
604 *
605 * f7fc0000 - f7ffffff Sec FDT (256KB)
606 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
607 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
608 * f6f00000 - f7efffff Sec OS image (16MB)
609 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
610 */
611#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000)
612#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000)
613#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000)
614#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000)
615#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
616#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
617
618#define CONFIG_PROG_UBOOT1 \
619 "$download_cmd $loadaddr $ubootfile; " \
620 "if test $? -eq 0; then " \
621 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
622 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
623 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
624 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
625 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
626 "if test $? -ne 0; then " \
627 "echo PROGRAM FAILED; " \
628 "else; " \
629 "echo PROGRAM SUCCEEDED; " \
630 "fi; " \
631 "else; " \
632 "echo DOWNLOAD FAILED; " \
633 "fi;"
634
635#define CONFIG_PROG_UBOOT2 \
636 "$download_cmd $loadaddr $ubootfile; " \
637 "if test $? -eq 0; then " \
638 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
639 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
640 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
641 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
642 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
643 "if test $? -ne 0; then " \
644 "echo PROGRAM FAILED; " \
645 "else; " \
646 "echo PROGRAM SUCCEEDED; " \
647 "fi; " \
648 "else; " \
649 "echo DOWNLOAD FAILED; " \
650 "fi;"
651
652#define CONFIG_BOOT_OS_NET \
653 "$download_cmd $osaddr $osfile; " \
654 "if test $? -eq 0; then " \
655 "if test -n $fdtaddr; then " \
656 "$download_cmd $fdtaddr $fdtfile; " \
657 "if test $? -eq 0; then " \
658 "bootm $osaddr - $fdtaddr; " \
659 "else; " \
660 "echo FDT DOWNLOAD FAILED; " \
661 "fi; " \
662 "else; " \
663 "bootm $osaddr; " \
664 "fi; " \
665 "else; " \
666 "echo OS DOWNLOAD FAILED; " \
667 "fi;"
668
669#define CONFIG_PROG_OS1 \
670 "$download_cmd $osaddr $osfile; " \
671 "if test $? -eq 0; then " \
672 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
673 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
674 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
675 "if test $? -ne 0; then " \
676 "echo OS PROGRAM FAILED; " \
677 "else; " \
678 "echo OS PROGRAM SUCCEEDED; " \
679 "fi; " \
680 "else; " \
681 "echo OS DOWNLOAD FAILED; " \
682 "fi;"
683
684#define CONFIG_PROG_OS2 \
685 "$download_cmd $osaddr $osfile; " \
686 "if test $? -eq 0; then " \
687 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
688 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
689 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
690 "if test $? -ne 0; then " \
691 "echo OS PROGRAM FAILED; " \
692 "else; " \
693 "echo OS PROGRAM SUCCEEDED; " \
694 "fi; " \
695 "else; " \
696 "echo OS DOWNLOAD FAILED; " \
697 "fi;"
698
699#define CONFIG_PROG_FDT1 \
700 "$download_cmd $fdtaddr $fdtfile; " \
701 "if test $? -eq 0; then " \
702 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
703 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
704 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
705 "if test $? -ne 0; then " \
706 "echo FDT PROGRAM FAILED; " \
707 "else; " \
708 "echo FDT PROGRAM SUCCEEDED; " \
709 "fi; " \
710 "else; " \
711 "echo FDT DOWNLOAD FAILED; " \
712 "fi;"
713
714#define CONFIG_PROG_FDT2 \
715 "$download_cmd $fdtaddr $fdtfile; " \
716 "if test $? -eq 0; then " \
717 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
718 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
719 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
720 "if test $? -ne 0; then " \
721 "echo FDT PROGRAM FAILED; " \
722 "else; " \
723 "echo FDT PROGRAM SUCCEEDED; " \
724 "fi; " \
725 "else; " \
726 "echo FDT DOWNLOAD FAILED; " \
727 "fi;"
728
729#define CONFIG_EXTRA_ENV_SETTINGS \
730 "autoload=yes\0" \
731 "download_cmd=tftp\0" \
732 "console_args=console=ttyS0,115200\0" \
733 "root_args=root=/dev/nfs rw\0" \
734 "misc_args=ip=on\0" \
735 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
736 "bootfile=/home/user/file\0" \
737 "osfile=/home/user/uImage-XPedite5170\0" \
738 "fdtfile=/home/user/xpedite5170.dtb\0" \
739 "ubootfile=/home/user/u-boot.bin\0" \
740 "fdtaddr=c00000\0" \
741 "osaddr=0x1000000\0" \
742 "loadaddr=0x1000000\0" \
743 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
744 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
745 "prog_os1="CONFIG_PROG_OS1"\0" \
746 "prog_os2="CONFIG_PROG_OS2"\0" \
747 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
748 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
749 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
750 "bootcmd_flash1=run set_bootargs; " \
751 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
752 "bootcmd_flash2=run set_bootargs; " \
753 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
754 "bootcmd=run bootcmd_flash1\0"
755#endif /* __CONFIG_H */