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Jon Loeliger0cde4b02007-04-11 16:50:57 -05001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
Jon Loeliger0cde4b02007-04-11 16:50:57 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Jon Loeliger0cde4b02007-04-11 16:50:57 -05005 */
6
7/*
8 * mpc8544ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/* High Level Configuration Options */
15#define CONFIG_BOOKE 1 /* BOOKE */
16#define CONFIG_E500 1 /* BOOKE e500 family */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050017#define CONFIG_MPC8544 1
18#define CONFIG_MPC8544DS 1
19
Wolfgang Denk2ae18242010-10-06 09:05:45 +020020#ifndef CONFIG_SYS_TEXT_BASE
21#define CONFIG_SYS_TEXT_BASE 0xfff80000
22#endif
23
Ed Swarthout837f1ba2007-07-27 01:50:51 -050024#define CONFIG_PCI 1 /* Enable PCI/PCIE */
25#define CONFIG_PCI1 1 /* PCI controller 1 */
26#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
27#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
28#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
29#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000030#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala8ff3de62007-12-07 12:17:34 -060031#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050032#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050033
Kumar Gala4bcae9c2008-01-16 01:16:16 -060034#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Roy Zangf6155c62009-07-09 10:05:48 +080035#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
Kumar Gala4bcae9c2008-01-16 01:16:16 -060036
Ed Swarthout837f1ba2007-07-27 01:50:51 -050037#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050038#define CONFIG_ENV_OVERWRITE
Ed Swarthout837f1ba2007-07-27 01:50:51 -050039#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050040
Jon Loeliger0cde4b02007-04-11 16:50:57 -050041#ifndef __ASSEMBLY__
42extern unsigned long get_board_sys_clk(unsigned long dummy);
43#endif
44#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
45
46/*
47 * These can be toggled for performance analysis, otherwise use default.
48 */
Ed Swarthout837f1ba2007-07-27 01:50:51 -050049#define CONFIG_L2_CACHE /* toggle L2 cache */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050050#define CONFIG_BTB /* toggle branch predition */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050051
52/*
53 * Only possible on E500 Version 2 or newer cores.
54 */
55#define CONFIG_ENABLE_36BIT_PHYS 1
56
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
58#define CONFIG_SYS_MEMTEST_END 0x00400000
Ed Swarthout837f1ba2007-07-27 01:50:51 -050059#define CONFIG_PANIC_HANG /* do not reset board on panic */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050060
Timur Tabie46fedf2011-08-04 18:03:41 -050061#define CONFIG_SYS_CCSRBAR 0xe0000000
62#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Jon Loeliger0cde4b02007-04-11 16:50:57 -050063
Kumar Gala1167a2f2008-08-26 08:02:30 -050064/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070065#define CONFIG_SYS_FSL_DDR2
Kumar Gala1167a2f2008-08-26 08:02:30 -050066#undef CONFIG_FSL_DDR_INTERACTIVE
67#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
68#define CONFIG_DDR_SPD
Jon Loeliger0cde4b02007-04-11 16:50:57 -050069
Dave Liu9b0ad1b2008-10-28 17:53:38 +080070#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala1167a2f2008-08-26 08:02:30 -050071#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
74#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala1167a2f2008-08-26 08:02:30 -050075#define CONFIG_VERY_BIG_RAM
76
77#define CONFIG_NUM_DDR_CONTROLLERS 1
78#define CONFIG_DIMM_SLOTS_PER_CTLR 1
79#define CONFIG_CHIP_SELECTS_PER_CTRL 2
80
81/* I2C addresses of SPD EEPROMs */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050082#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
83
Kumar Gala1167a2f2008-08-26 08:02:30 -050084/* Make sure required options are set */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050085#ifndef CONFIG_SPD_EEPROM
86#error ("CONFIG_SPD_EEPROM is required")
87#endif
88
89#undef CONFIG_CLOCKS_IN_MHZ
90
91/*
92 * Memory map
93 *
94 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
95 *
96 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
97 *
98 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
99 *
100 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
101 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
102 *
103 * Localbus cacheable
104 *
105 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
106 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
107 *
108 * Localbus non-cacheable
109 *
110 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
111 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
112 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
113 *
114 */
115
116/*
117 * Local Bus Definitions
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_BR0_PRELIM 0xff801001
124#define CONFIG_SYS_BR1_PRELIM 0xfe801001
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_OR0_PRELIM 0xff806e65
127#define CONFIG_SYS_OR1_PRELIM 0xff806e65
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_FLASH_QUIET_TEST
132#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
133#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
134#undef CONFIG_SYS_FLASH_CHECKSUM
135#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
136#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala81e56e92008-06-09 18:55:38 -0500137#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500138
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200139#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500140
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200141#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_FLASH_CFI
143#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
148#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
151#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500152
Kim Phillips7608d752007-08-21 17:00:17 -0500153#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500154#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
155#define PIXIS_ID 0x0 /* Board ID at offset 0 */
156#define PIXIS_VER 0x1 /* Board version at offset 1 */
157#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
158#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
159#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
160 * register */
161#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
162#define PIXIS_VCTL 0x10 /* VELA Control Register */
163#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
164#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
165#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500166#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
167#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500168#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
169#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
170#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
171#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Andy Fleming5a8a1632008-08-31 16:33:30 -0500172#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Andy Fleming5a8a1632008-08-31 16:33:30 -0500174#define PIXIS_VSPEED2_TSEC1SER 0x2
175#define PIXIS_VSPEED2_TSEC3SER 0x1
176#define PIXIS_VCFGEN1_TSEC1SER 0x20
177#define PIXIS_VCFGEN1_TSEC3SER 0x40
Liu Yubff188b2008-10-10 11:40:58 +0800178#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
179#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500180
181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_INIT_RAM_LOCK 1
183#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200184#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500185
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500186
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200187#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
191#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500192
193/* Serial Port - controlled on board with jumper J8
194 * open - index 2
195 * shorted - index 1
196 */
197#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_NS16550
199#define CONFIG_SYS_NS16550_SERIAL
200#define CONFIG_SYS_NS16550_REG_SIZE 1
201#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500204 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
207#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500208
209/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_HUSH_PARSER
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500211
212/* pass open firmware flat tree */
Kumar Galaaddce572007-11-26 17:12:24 -0600213#define CONFIG_OF_LIBFDT 1
214#define CONFIG_OF_BOARD_SETUP 1
215#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500216
217/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200218#define CONFIG_SYS_I2C
219#define CONFIG_SYS_I2C_FSL
220#define CONFIG_SYS_FSL_I2C_SPEED 400000
221#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
222#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
223#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500225
226/*
227 * General PCI
228 * Memory space is mapped 1-1, but I/O space must start from 0.
229 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600230#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600232#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500234
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600235#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600236#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600237#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600239#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600240#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
242#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500243
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500244/* controller 2, Slot 1, tgtid 1, Base address 9000 */
Kumar Gala64a16862010-12-17 06:01:24 -0600245#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600246#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600247#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600248#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600250#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600251#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
253#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500254
255/* controller 1, Slot 2,tgtid 2, Base address a000 */
Kumar Gala64a16862010-12-17 06:01:24 -0600256#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600257#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600258#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600259#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600261#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600262#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
264#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500265
266/* controller 3, direct to uli, tgtid 3, Base address b000 */
Kumar Gala64a16862010-12-17 06:01:24 -0600267#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600268#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600269#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600270#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600272#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
Kumar Gala5f91ef62008-12-02 16:08:37 -0600273#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
275#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600276#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
Kumar Gala10795f42008-12-02 16:08:36 -0600277#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600278#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500280
281#if defined(CONFIG_PCI)
282
Kumar Gala630d9bf2008-07-14 14:07:03 -0500283/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600284#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
Kumar Gala630d9bf2008-07-14 14:07:03 -0500285
286/*PCI video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600287/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala630d9bf2008-07-14 14:07:03 -0500288
289/* video */
290#define CONFIG_VIDEO
291
292#if defined(CONFIG_VIDEO)
293#define CONFIG_BIOSEMU
294#define CONFIG_CFB_CONSOLE
295#define CONFIG_VIDEO_SW_CURSOR
296#define CONFIG_VGA_AS_SINGLE_DEVICE
297#define CONFIG_ATI_RADEON_FB
298#define CONFIG_VIDEO_LOGO
299/*#define CONFIG_CONSOLE_CURSOR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala630d9bf2008-07-14 14:07:03 -0500301#endif
302
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500303#define CONFIG_PCI_PNP /* do pci plug-and-play */
304
305#undef CONFIG_EEPRO100
306#undef CONFIG_TULIP
307#define CONFIG_RTL8139
308
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500309#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600310 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
311 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500312 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
313#endif
314
315#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
316#define CONFIG_DOS_PARTITION
317#define CONFIG_SCSI_AHCI
318
319#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -0500320#define CONFIG_LIBATA
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500321#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
323#define CONFIG_SYS_SCSI_MAX_LUN 1
324#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
325#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500326#endif /* SCSCI */
327
328#endif /* CONFIG_PCI */
329
330
331#if defined(CONFIG_TSEC_ENET)
332
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500333#define CONFIG_MII 1 /* MII PHY management */
334#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
Kim Phillips255a35772007-05-16 16:52:19 -0500335#define CONFIG_TSEC1 1
336#define CONFIG_TSEC1_NAME "eTSEC1"
337#define CONFIG_TSEC3 1
338#define CONFIG_TSEC3_NAME "eTSEC3"
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500339
Liu Yubff188b2008-10-10 11:40:58 +0800340#define CONFIG_PIXIS_SGMII_CMD
Andy Fleming652f7c22008-08-31 16:33:28 -0500341#define CONFIG_FSL_SGMII_RISER 1
342#define SGMII_RISER_PHY_OFFSET 0x1c
343
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500344#define TSEC1_PHY_ADDR 0
345#define TSEC3_PHY_ADDR 1
346
Andy Fleming3a790132007-08-15 20:03:25 -0500347#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
348#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
349
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500350#define TSEC1_PHYIDX 0
351#define TSEC3_PHYIDX 0
352
353#define CONFIG_ETHPRIME "eTSEC1"
354
355#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500356#endif /* CONFIG_TSEC_ENET */
357
358/*
359 * Environment
360 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200361#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200363#define CONFIG_ENV_ADDR 0xfff80000
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500364#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500366#endif
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200367#define CONFIG_ENV_SIZE 0x2000
368#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500369
370#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500372
Jon Loeliger2835e512007-06-13 13:22:08 -0500373/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500374 * BOOTP options
375 */
376#define CONFIG_BOOTP_BOOTFILESIZE
377#define CONFIG_BOOTP_BOOTPATH
378#define CONFIG_BOOTP_GATEWAY
379#define CONFIG_BOOTP_HOSTNAME
380
381
382/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500383 * Command line configuration.
384 */
385#include <config_cmd_default.h>
386
387#define CONFIG_CMD_PING
388#define CONFIG_CMD_I2C
389#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600390#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500391#define CONFIG_CMD_IRQ
392#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500393#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500394
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500395#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500396 #define CONFIG_CMD_PCI
Jon Loeliger2835e512007-06-13 13:22:08 -0500397 #define CONFIG_CMD_NET
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500398 #define CONFIG_CMD_SCSI
399 #define CONFIG_CMD_EXT2
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500400#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500401
Hongtao Jia86a194b2012-12-20 19:39:53 +0000402/*
403 * USB
404 */
405#define CONFIG_USB_EHCI
406
407#ifdef CONFIG_USB_EHCI
408#define CONFIG_CMD_USB
409#define CONFIG_USB_EHCI_PCI
410#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
411#define CONFIG_USB_STORAGE
412#define CONFIG_PCI_EHCI_DEVICE 0
413#endif
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500414
415#undef CONFIG_WATCHDOG /* watchdog disabled */
416
417/*
418 * Miscellaneous configurable options
419 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500421#define CONFIG_CMDLINE_EDITING /* Command-line editing */
422#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeliger2835e512007-06-13 13:22:08 -0500424#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500426#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500428#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
430#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
431#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500432
433/*
434 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500435 * have to be in the first 64 MB of memory, since this is
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500436 * the maximum mapped by the Linux kernel during initialization.
437 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500438#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
439#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500440
Jon Loeliger2835e512007-06-13 13:22:08 -0500441#if defined(CONFIG_CMD_KGDB)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500442#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500443#endif
444
445/*
446 * Environment Configuration
447 */
448
449/* The mac addresses for all ethernet interface */
450#if defined(CONFIG_TSEC_ENET)
Kumar Galaea5877e2007-08-16 11:01:21 -0500451#define CONFIG_HAS_ETH0
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500452#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
453#define CONFIG_HAS_ETH1
454#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500455#endif
456
457#define CONFIG_IPADDR 192.168.1.251
458
459#define CONFIG_HOSTNAME 8544ds_unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000460#define CONFIG_ROOTPATH "/nfs/mpc85xx"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000461#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500462#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500463
Kumar Gala50c03c82007-11-27 22:42:34 -0600464#define CONFIG_SERVERIP 192.168.1.1
465#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500466#define CONFIG_NETMASK 255.255.0.0
467
468#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
469
470#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500471#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500472
473#define CONFIG_BAUDRATE 115200
474
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500475#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200476"netdev=eth0\0" \
477"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
478"tftpflash=tftpboot $loadaddr $uboot; " \
479 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
480 " +$filesize; " \
481 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
482 " +$filesize; " \
483 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
484 " $filesize; " \
485 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
486 " +$filesize; " \
487 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
488 " $filesize\0" \
489"consoledev=ttyS0\0" \
490"ramdiskaddr=2000000\0" \
491"ramdiskfile=8544ds/ramdisk.uboot\0" \
492"fdtaddr=c00000\0" \
493"fdtfile=8544ds/mpc8544ds.dtb\0" \
494"bdev=sda3\0"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500495
496#define CONFIG_NFSBOOTCOMMAND \
497 "setenv bootargs root=/dev/nfs rw " \
498 "nfsroot=$serverip:$rootpath " \
499 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
500 "console=$consoledev,$baudrate $othbootargs;" \
501 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600502 "tftp $fdtaddr $fdtfile;" \
503 "bootm $loadaddr - $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500504
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500505#define CONFIG_RAMBOOTCOMMAND \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500506 "setenv bootargs root=/dev/ram rw " \
507 "console=$consoledev,$baudrate $othbootargs;" \
508 "tftp $ramdiskaddr $ramdiskfile;" \
509 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600510 "tftp $fdtaddr $fdtfile;" \
511 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500512
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500513#define CONFIG_BOOTCOMMAND \
514 "setenv bootargs root=/dev/$bdev rw " \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500515 "console=$consoledev,$baudrate $othbootargs;" \
516 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600517 "tftp $fdtaddr $fdtfile;" \
518 "bootm $loadaddr - $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500519
520#endif /* __CONFIG_H */