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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk0f8c9762002-08-19 11:57:05 +00006 */
7
8/*
9 * Config header file for Cogent platform using an MPC8xx CPU module
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
21#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050022#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk0f8c9762002-08-19 11:57:05 +000023
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0xfff00000
25
wdenkc837dcb2004-01-20 23:12:12 +000026#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050027#define CONFIG_MISC_INIT_R /* Use misc_init_r() */
wdenkc837dcb2004-01-20 23:12:12 +000028
wdenk0f8c9762002-08-19 11:57:05 +000029/* Cogent Modular Architecture options */
30#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */
31#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */
32
33/*
34 * select serial console configuration
35 *
36 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
37 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
38 * for SCC).
39 *
40 * if CONFIG_CONS_NONE is defined, then the serial console routines must
41 * defined elsewhere (for example, on the cogent platform, there are serial
42 * ports on the motherboard which are used for the serial console - see
43 * cogent/cma101/serial.[ch]).
44 */
45#define CONFIG_CONS_ON_SMC /* define if console on SMC */
46#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
47#undef CONFIG_CONS_NONE /* define if console on something else*/
48#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
49#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
50#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
51#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
52
53/*
54 * select ethernet configuration
55 *
56 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
57 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
58 * for FCC)
59 *
60 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050061 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk0f8c9762002-08-19 11:57:05 +000062 */
63#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
64#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
65#define CONFIG_ETHER_NONE /* define if ether on something else */
66#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
67
68/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
69#define CONFIG_8260_CLKIN 66666666 /* in Hz */
70
71#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
72#define CONFIG_BAUDRATE 230400
73#else
74#define CONFIG_BAUDRATE 9600
75#endif
76
wdenk0f8c9762002-08-19 11:57:05 +000077
Jon Loeliger37e4f242007-07-04 22:31:56 -050078/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050079 * BOOTP options
80 */
81#define CONFIG_BOOTP_BOOTFILESIZE
82#define CONFIG_BOOTP_BOOTPATH
83#define CONFIG_BOOTP_GATEWAY
84#define CONFIG_BOOTP_HOSTNAME
85
86
87/*
Jon Loeliger37e4f242007-07-04 22:31:56 -050088 * Command line configuration.
89 */
90#include <config_cmd_default.h>
91
92#define CONFIG_CMD_KGDB
93
94#undef CONFIG_CMD_NET
Wolfgang Denkba273f02010-11-24 19:19:08 +010095#undef CONFIG_CMD_NFS
wdenk0f8c9762002-08-19 11:57:05 +000096
97#ifdef DEBUG
98#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
99#else
100#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
101#endif
102#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
103
104#define CONFIG_BOOTARGS "root=/dev/ram rw"
105
Jon Loeliger37e4f242007-07-04 22:31:56 -0500106#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000107#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
108#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
109#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
110#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
111#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
112#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
113#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
114# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
115#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
116# else
117#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
118# endif
119#endif
120
121#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
122
123/*
124 * Miscellaneous configurable options
125 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500127#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000129#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000131#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
133#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
134#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
137#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk0f8c9762002-08-19 11:57:05 +0000142
143/*
144 * Low Level Configuration Settings
145 * (address mappings, register initial values, etc.)
146 * You should know what you are doing if you make changes here.
147 */
148
149/*-----------------------------------------------------------------------
150 * Low Level Cogent settings
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151 * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
wdenk0f8c9762002-08-19 11:57:05 +0000152 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
153 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
154 * (second 2 for CMA120 only)
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */
wdenk0f8c9762002-08-19 11:57:05 +0000157
158#include <configs/cogent_common.h>
159
160#ifdef CONFIG_CONS_NONE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
wdenk0f8c9762002-08-19 11:57:05 +0000162#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
wdenka8c7c702003-12-06 19:49:23 +0000164#define CONFIG_SHOW_ACTIVITY
wdenk0f8c9762002-08-19 11:57:05 +0000165
166#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
167/*
168 * flash exists on the motherboard
169 * set these four according to TOP dipsw:
170 * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
171 * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
172 */
173#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
174#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
175#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
176#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
177#endif
178#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
179#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
180
181/*-----------------------------------------------------------------------
182 * Hard Reset Configuration Words
183 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenk0f8c9762002-08-19 11:57:05 +0000185 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenk0f8c9762002-08-19 11:57:05 +0000187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
wdenk0f8c9762002-08-19 11:57:05 +0000189 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
190/* no slaves so just duplicate the master hrcw */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
192#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
193#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
194#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
195#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
196#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
197#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
wdenk0f8c9762002-08-19 11:57:05 +0000198
199/*-----------------------------------------------------------------------
200 * Internal Memory Mapped Register
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_IMMR 0xF0000000
wdenk0f8c9762002-08-19 11:57:05 +0000203
204/*-----------------------------------------------------------------------
205 * Definitions for initial stack pointer and data area (in DPRAM)
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200208#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200209#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000211
212/*-----------------------------------------------------------------------
213 * Start addresses for the final memory configuration
214 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE
wdenk0f8c9762002-08-19 11:57:05 +0000218#ifdef CONFIG_CMA302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
wdenk0f8c9762002-08-19 11:57:05 +0000220#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
wdenk0f8c9762002-08-19 11:57:05 +0000222#endif
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200223#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
225#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
wdenk0f8c9762002-08-19 11:57:05 +0000226
227/*
228 * For booting Linux, the board info and command line data
229 * have to be in the first 8 MB of memory, since this is
230 * the maximum mapped by the Linux kernel during initialization.
231 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
wdenk0f8c9762002-08-19 11:57:05 +0000233
234/*-----------------------------------------------------------------------
235 * FLASH organization
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
238#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
241#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000242
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200243#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000245#ifdef CONFIG_CMA302
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200246#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
247#define CONFIG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
wdenk0f8c9762002-08-19 11:57:05 +0000248#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200249#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000250#endif
251
252/*-----------------------------------------------------------------------
253 * Cache Configuration
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500256#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
wdenk0f8c9762002-08-19 11:57:05 +0000258#endif
259
260/*-----------------------------------------------------------------------
261 * HIDx - Hardware Implementation-dependent Registers 2-11
262 *-----------------------------------------------------------------------
263 * HID0 also contains cache control - initially enable both caches and
264 * invalidate contents, then the final state leaves only the instruction
265 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
266 * but Soft reset does not.
267 *
268 * HID1 has only read-only information - nothing to set.
269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
wdenk0f8c9762002-08-19 11:57:05 +0000271 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
273#define CONFIG_SYS_HID2 0
wdenk0f8c9762002-08-19 11:57:05 +0000274
275/*-----------------------------------------------------------------------
276 * RMR - Reset Mode Register 5-5
277 *-----------------------------------------------------------------------
278 * turn on Checkstop Reset Enable
279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_RMR RMR_CSRE
wdenk0f8c9762002-08-19 11:57:05 +0000281
282/*-----------------------------------------------------------------------
283 * BCR - Bus Configuration 4-25
284 *-----------------------------------------------------------------------
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_BCR BCR_EBM
wdenk0f8c9762002-08-19 11:57:05 +0000287
288/*-----------------------------------------------------------------------
289 * SIUMCR - SIU Module Configuration 4-31
290 *-----------------------------------------------------------------------
291 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
wdenk0f8c9762002-08-19 11:57:05 +0000293
294/*-----------------------------------------------------------------------
295 * SYPCR - System Protection Control 4-35
296 * SYPCR can only be written once after reset!
297 *-----------------------------------------------------------------------
298 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
299 */
300#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk0f8c9762002-08-19 11:57:05 +0000302 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
303#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk0f8c9762002-08-19 11:57:05 +0000305 SYPCR_SWRI|SYPCR_SWP)
306#endif /* CONFIG_WATCHDOG */
307
308/*-----------------------------------------------------------------------
309 * TMCNTSC - Time Counter Status and Control 4-40
310 *-----------------------------------------------------------------------
311 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
312 * and enable Time Counter
313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenk0f8c9762002-08-19 11:57:05 +0000315
316/*-----------------------------------------------------------------------
317 * PISCR - Periodic Interrupt Status and Control 4-42
318 *-----------------------------------------------------------------------
319 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
320 * Periodic timer
321 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenk0f8c9762002-08-19 11:57:05 +0000323
324/*-----------------------------------------------------------------------
325 * SCCR - System Clock Control 9-8
326 *-----------------------------------------------------------------------
327 * Ensure DFBRG is Divide by 16
328 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
wdenk0f8c9762002-08-19 11:57:05 +0000330
331/*-----------------------------------------------------------------------
332 * RCCR - RISC Controller Configuration 13-7
333 *-----------------------------------------------------------------------
334 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_RCCR 0
wdenk0f8c9762002-08-19 11:57:05 +0000336
337#if defined(CONFIG_CMA282)
338
339/*
340 * Init Memory Controller:
341 *
342 * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
343 * and CS2 for (optional) local bus RAM on the CPU module.
344 *
345 * Note the motherboard address space (256 Mbyte in size) is connected
346 * to the 60x Bus and is located starting at address 0. The Hard Reset
347 * Configuration Word should put the 60x Bus into External Bus Mode, since
348 * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
349 *
350 * (the *_SIZE vars must be a power of 2)
351 */
352
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200353#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
wdenk0f8c9762002-08-19 11:57:05 +0000355#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
357#define CONFIG_SYS_CMA_CS2_SIZE (16 << 20)
wdenk0f8c9762002-08-19 11:57:05 +0000358#endif
359
360/*
361 * CS0 maps the EPROM on the cpu module
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362 * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
wdenk0f8c9762002-08-19 11:57:05 +0000363 *
364 * Note: We must have already transferred control to the final location
365 * of the EPROM before these are used, because when BR0/OR0 are set, the
366 * mirror of the eprom at any other addresses will disappear.
367 */
368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
370#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
371/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
372#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
wdenk0f8c9762002-08-19 11:57:05 +0000373 ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
374
375/*
376 * CS2 enables the Local Bus SDRAM on the CPU Module
377 *
378 * Will leave this unset for the moment, because a) my CPU module has no
379 * SDRAM installed (it is optional); and b) it will require programming
380 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
381 * if you can't test it.
382 */
383
384#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
386#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
387/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
388#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
wdenk0f8c9762002-08-19 11:57:05 +0000389#endif
390
391#endif
wdenk0f8c9762002-08-19 11:57:05 +0000392#endif /* __CONFIG_H */