blob: 6469a919f6df1f5b854ff9369dcf51d079e1d132 [file] [log] [blame]
Alison Wang186fc4d2012-10-18 19:25:52 +00001/*
2 * Configuation settings for the Freescale MCF54418 TWR board.
3 *
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Alison Wang186fc4d2012-10-18 19:25:52 +00008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M54418TWR_H
15#define _M54418TWR_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
Alison Wang186fc4d2012-10-18 19:25:52 +000021#define CONFIG_M54418TWR /* M54418TWR board */
22
23#define CONFIG_MCFUART
24#define CONFIG_SYS_UART_PORT (0)
Alison Wang186fc4d2012-10-18 19:25:52 +000025#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
26
Angelo Dureghelloc74dda82017-05-14 21:42:27 +020027#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
28
Alison Wang186fc4d2012-10-18 19:25:52 +000029#undef CONFIG_WATCHDOG
30
31#define CONFIG_TIMESTAMP /* Print image info with timestamp */
32
33/*
34 * BOOTP options
35 */
36#define CONFIG_BOOTP_BOOTFILESIZE
37#define CONFIG_BOOTP_BOOTPATH
38#define CONFIG_BOOTP_GATEWAY
39#define CONFIG_BOOTP_HOSTNAME
40
Alison Wang186fc4d2012-10-18 19:25:52 +000041/*
42 * NAND FLASH
43 */
44#ifdef CONFIG_CMD_NAND
45#define CONFIG_JFFS2_NAND
46#define CONFIG_NAND_FSL_NFC
47#define CONFIG_SYS_NAND_BASE 0xFC0FC000
48#define CONFIG_SYS_MAX_NAND_DEVICE 1
49#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
50#define CONFIG_SYS_NAND_SELECT_DEVICE
Alison Wang186fc4d2012-10-18 19:25:52 +000051#endif
52
53/* Network configuration */
54#define CONFIG_MCFFEC
55#ifdef CONFIG_MCFFEC
Alison Wang186fc4d2012-10-18 19:25:52 +000056#define CONFIG_MII 1
57#define CONFIG_MII_INIT 1
58#define CONFIG_SYS_DISCOVER_PHY
59#define CONFIG_SYS_RX_ETH_BUFFER 2
Lothar Waßmanne34b9132017-05-18 17:26:58 +020060#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Alison Wang186fc4d2012-10-18 19:25:52 +000061#define CONFIG_SYS_TX_ETH_BUFFER 2
62#define CONFIG_HAS_ETH1
63
64#define CONFIG_SYS_FEC0_PINMUX 0
65#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
66#define CONFIG_SYS_FEC1_PINMUX 0
67#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
68#define MCFFEC_TOUT_LOOP 50000
69#define CONFIG_SYS_FEC0_PHYADDR 0
70#define CONFIG_SYS_FEC1_PHYADDR 1
71
Alison Wang186fc4d2012-10-18 19:25:52 +000072#define CONFIG_ETHPRIME "FEC0"
73#define CONFIG_IPADDR 192.168.1.2
74#define CONFIG_NETMASK 255.255.255.0
75#define CONFIG_SERVERIP 192.168.1.1
76#define CONFIG_GATEWAYIP 192.168.1.1
77
Alison Wang186fc4d2012-10-18 19:25:52 +000078#define CONFIG_SYS_FEC_BUF_USE_SRAM
79/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
80#ifndef CONFIG_SYS_DISCOVER_PHY
81#define FECDUPLEX FULL
82#define FECSPEED _100BASET
83#define LINKSTATUS 1
84#else
85#define LINKSTATUS 0
86#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
87#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
88#endif
89#endif /* CONFIG_SYS_DISCOVER_PHY */
90#endif
91
92#define CONFIG_HOSTNAME M54418TWR
93
94#if defined(CONFIG_CF_SBF)
95/* ST Micro serial flash */
96#define CONFIG_SYS_LOAD_ADDR2 0x40010007
97#define CONFIG_EXTRA_ENV_SETTINGS \
98 "netdev=eth0\0" \
99 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
100 "loadaddr=0x40010000\0" \
101 "sbfhdr=sbfhdr.bin\0" \
102 "uboot=u-boot.bin\0" \
103 "load=tftp ${loadaddr} ${sbfhdr};" \
104 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
105 "upd=run load; run prog\0" \
106 "prog=sf probe 0:1 1000000 3;" \
107 "sf erase 0 40000;" \
108 "sf write ${loadaddr} 0 40000;" \
109 "save\0" \
110 ""
111#elif defined(CONFIG_SYS_NAND_BOOT)
112#define CONFIG_EXTRA_ENV_SETTINGS \
113 "netdev=eth0\0" \
114 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
115 "loadaddr=0x40010000\0" \
116 "u-boot=u-boot.bin\0" \
117 "load=tftp ${loadaddr} ${u-boot};\0" \
118 "upd=run load; run prog\0" \
119 "prog=nand device 0;" \
120 "nand erase 0 40000;" \
121 "nb_update ${loadaddr} ${filesize};" \
122 "save\0" \
123 ""
124#else
125#define CONFIG_SYS_UBOOT_END 0x3FFFF
126#define CONFIG_EXTRA_ENV_SETTINGS \
127 "netdev=eth0\0" \
128 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
129 "loadaddr=40010000\0" \
130 "u-boot=u-boot.bin\0" \
131 "load=tftp ${loadaddr) ${u-boot}\0" \
132 "upd=run load; run prog\0" \
133 "prog=prot off mram" " ;" \
134 "cp.b ${loadaddr} 0 ${filesize};" \
135 "save\0" \
136 ""
137#endif
138
139/* Realtime clock */
140#undef CONFIG_MCFRTC
141#define CONFIG_RTC_MCFRRTC
142#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
143
144/* Timer */
145#define CONFIG_MCFTMR
146#undef CONFIG_MCFPIT
147
148/* I2c */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200149#undef CONFIG_SYS_FSL_I2C
Heiko Schocherea818db2013-01-29 08:53:15 +0100150#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
Alison Wang186fc4d2012-10-18 19:25:52 +0000151/* I2C speed and slave address */
152#define CONFIG_SYS_I2C_SPEED 80000
153#define CONFIG_SYS_I2C_SLAVE 0x7F
154#define CONFIG_SYS_I2C_OFFSET 0x58000
155#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
156
157/* DSPI and Serial Flash */
158#define CONFIG_CF_SPI
159#define CONFIG_CF_DSPI
160#define CONFIG_SERIAL_FLASH
161#define CONFIG_HARD_SPI
162#define CONFIG_SYS_SBFHDR_SIZE 0x7
163#ifdef CONFIG_CMD_SPI
Alison Wang186fc4d2012-10-18 19:25:52 +0000164
165# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
166 DSPI_CTAR_PCSSCK_1CLK | \
167 DSPI_CTAR_PASC(0) | \
168 DSPI_CTAR_PDT(0) | \
169 DSPI_CTAR_CSSCK(0) | \
170 DSPI_CTAR_ASC(0) | \
171 DSPI_CTAR_DT(1))
172# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
173# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
174#endif
175
176/* Input, PCI, Flexbus, and VCO */
177#define CONFIG_EXTRA_CLOCK
178
179#define CONFIG_PRAM 2048 /* 2048 KB */
180
Alison Wang186fc4d2012-10-18 19:25:52 +0000181#define CONFIG_SYS_LONGHELP /* undef to save memory */
182
Alison Wang186fc4d2012-10-18 19:25:52 +0000183#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
184
Alison Wang186fc4d2012-10-18 19:25:52 +0000185#define CONFIG_SYS_MBAR 0xFC000000
186
187/*
188 * Low Level Configuration Settings
189 * (address mappings, register initial values, etc.)
190 * You should know what you are doing if you make changes here.
191 */
192
193/*-----------------------------------------------------------------------
194 * Definitions for initial stack pointer and data area (in DPRAM)
195 */
196#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
197/* End of used area in internal SRAM */
198#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
199#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Alison Wang186fc4d2012-10-18 19:25:52 +0000200#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900201 GENERATED_GBL_DATA_SIZE) - 32)
Alison Wang186fc4d2012-10-18 19:25:52 +0000202#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
203#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
204
205/*-----------------------------------------------------------------------
206 * Start addresses for the final memory configuration
207 * (Set up by the startup code)
208 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
209 */
210#define CONFIG_SYS_SDRAM_BASE 0x40000000
211#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
212
213#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
214#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
215#define CONFIG_SYS_DRAM_TEST
216
217#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
218#define CONFIG_SERIAL_BOOT
219#endif
220
221#if defined(CONFIG_SERIAL_BOOT)
Masahiro Yamada61a43922015-12-11 12:22:25 +0900222#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
Alison Wang186fc4d2012-10-18 19:25:52 +0000223#else
224#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
225#endif
226
227#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
228/* Reserve 256 kB for Monitor */
229#define CONFIG_SYS_MONITOR_LEN (256 << 10)
230/* Reserve 256 kB for malloc() */
231#define CONFIG_SYS_MALLOC_LEN (256 << 10)
232
233/*
234 * For booting Linux, the board info and command line data
235 * have to be in the first 8 MB of memory, since this is
236 * the maximum mapped by the Linux kernel during initialization ??
237 */
238/* Initial Memory map for Linux */
239#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
240 (CONFIG_SYS_SDRAM_SIZE << 20))
241
242/* Configuration for environment
243 * Environment is embedded in u-boot in the second sector of the flash
244 */
245#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
Alison Wang186fc4d2012-10-18 19:25:52 +0000246#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
247#define CONFIG_ENV_SIZE 0x1000
248#endif
249
250#if defined(CONFIG_CF_SBF)
Alison Wang186fc4d2012-10-18 19:25:52 +0000251#define CONFIG_ENV_SPI_CS 1
252#define CONFIG_ENV_OFFSET 0x40000
253#define CONFIG_ENV_SIZE 0x2000
254#define CONFIG_ENV_SECT_SIZE 0x10000
255#endif
256#if defined(CONFIG_SYS_NAND_BOOT)
Alison Wang186fc4d2012-10-18 19:25:52 +0000257#define CONFIG_ENV_OFFSET 0x80000
258#define CONFIG_ENV_SIZE 0x20000
259#define CONFIG_ENV_SECT_SIZE 0x20000
260#endif
261#undef CONFIG_ENV_OVERWRITE
262
263/* FLASH organization */
264#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
265
266#undef CONFIG_SYS_FLASH_CFI
267#ifdef CONFIG_SYS_FLASH_CFI
268
269#define CONFIG_FLASH_CFI_DRIVER 1
270/* Max size that the board might have */
271#define CONFIG_SYS_FLASH_SIZE 0x1000000
272#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
273/* max number of memory banks */
274#define CONFIG_SYS_MAX_FLASH_BANKS 1
275/* max number of sectors on one chip */
276#define CONFIG_SYS_MAX_FLASH_SECT 270
277/* "Real" (hardware) sectors protection */
278#define CONFIG_SYS_FLASH_PROTECTION
279#define CONFIG_SYS_FLASH_CHECKSUM
280#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
281#else
282/* max number of sectors on one chip */
283#define CONFIG_SYS_MAX_FLASH_SECT 270
284/* max number of sectors on one chip */
285#define CONFIG_SYS_MAX_FLASH_BANKS 0
286#endif
287
288/*
289 * This is setting for JFFS2 support in u-boot.
290 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
291 */
292#ifdef CONFIG_CMD_JFFS2
293#define CONFIG_JFFS2_DEV "nand0"
294#define CONFIG_JFFS2_PART_OFFSET (0x800000)
Alison Wang186fc4d2012-10-18 19:25:52 +0000295#define CONFIG_MTD_DEVICE
Alison Wang186fc4d2012-10-18 19:25:52 +0000296
297#endif
298
299#ifdef CONFIG_CMD_UBI
Alison Wang186fc4d2012-10-18 19:25:52 +0000300#define CONFIG_MTD_DEVICE /* needed for mtdparts command */
301#define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
Alison Wang186fc4d2012-10-18 19:25:52 +0000302#endif
303/* Cache Configuration */
304#define CONFIG_SYS_CACHELINE_SIZE 16
305#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
306 CONFIG_SYS_INIT_RAM_SIZE - 8)
307#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
308 CONFIG_SYS_INIT_RAM_SIZE - 4)
309#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
310#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
311#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
312 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
313 CF_ACR_EN | CF_ACR_SM_ALL)
314#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
315 CF_CACR_ICINVA | CF_CACR_EUSP)
316#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
317 CF_CACR_DEC | CF_CACR_DDCM_P | \
318 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
319
320#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
321 CONFIG_SYS_INIT_RAM_SIZE - 12)
322
323/*-----------------------------------------------------------------------
324 * Memory bank definitions
325 */
326/*
327 * CS0 - NOR Flash 16MB
328 * CS1 - Available
329 * CS2 - Available
330 * CS3 - Available
331 * CS4 - Available
332 * CS5 - Available
333 */
334
335 /* Flash */
336#define CONFIG_SYS_CS0_BASE 0x00000000
337#define CONFIG_SYS_CS0_MASK 0x000F0101
338#define CONFIG_SYS_CS0_CTRL 0x00001D60
339
340#endif /* _M54418TWR_H */