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wdenk5c952cf2004-10-10 21:27:30 +00001/*
2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include <asm/opcodes.h>
26
27
28 .text
29 .align 4
30
31 .global _exception
32
Scott McNuttc2ced002006-06-08 11:59:57 -040033 .set noat
34 .set nobreak
35
wdenk5c952cf2004-10-10 21:27:30 +000036_exception:
37 /* SAVE ALL REGS -- this allows trap and unimplemented
38 * instruction handlers to be coded conveniently in C
39 */
40 addi sp, sp, -(33*4)
41 stw r0, 0(sp)
42 stw r1, 4(sp)
43 stw r2, 8(sp)
44 stw r3, 12(sp)
45 stw r4, 16(sp)
46 stw r5, 20(sp)
47 stw r6, 24(sp)
48 stw r7, 28(sp)
49 stw r8, 32(sp)
50 stw r9, 36(sp)
51 stw r10, 40(sp)
52 stw r11, 44(sp)
53 stw r12, 48(sp)
54 stw r13, 52(sp)
55 stw r14, 56(sp)
56 stw r15, 60(sp)
57 stw r16, 64(sp)
58 stw r17, 68(sp)
59 stw r19, 72(sp)
60 stw r19, 76(sp)
61 stw r20, 80(sp)
62 stw r21, 84(sp)
63 stw r22, 88(sp)
64 stw r23, 92(sp)
65 stw r24, 96(sp)
66 stw r25, 100(sp)
67 stw r26, 104(sp)
68 stw r27, 108(sp)
69 stw r28, 112(sp)
70 stw r29, 116(sp)
71 stw r30, 120(sp)
72 stw r31, 124(sp)
73 rdctl et, estatus
74 stw et, 128(sp)
75
76 /* If interrupts are disabled -- software interrupt */
77 rdctl et, estatus
78 andi et, et, 1
79 beq et, r0, 0f
80
81 /* If no interrupts are pending -- software interrupt */
82 rdctl et, ipending
83 beq et, r0, 0f
84
85 /* HARDWARE INTERRUPT: Call interrupt handler */
86 movhi r3, %hi(external_interrupt)
87 ori r3, r3, %lo(external_interrupt)
88 mov r4, sp /* ptr to regs */
89 callr r3
90
91 /* Return address fixup: execution resumes by re-issue of
92 * interrupted instruction at ea-4 (ea == r29). Here we do
93 * simple fixup to allow common exception return.
94 */
95 ldw r3, 116(sp)
96 addi r3, r3, -4
97 stw r3, 116(sp)
98 br _exception_return
99
1000:
101 /* TRAP EXCEPTION */
102 movhi r3, %hi(OPC_TRAP)
103 ori r3, r3, %lo(OPC_TRAP)
104 addi r1, ea, -4
105 ldw r1, 0(r1)
106 bne r1, r3, 1f
107 movhi r3, %hi(trap_handler)
108 ori r3, r3, %lo(trap_handler)
109 mov r4, sp /* ptr to regs */
110 callr r3
111 br _exception_return
112
1131:
114 /* UNIMPLEMENTED INSTRUCTION EXCEPTION */
115 movhi r3, %hi(soft_emulation)
116 ori r3, r3, %lo(soft_emulation)
117 mov r4, sp /* ptr to regs */
118 callr r3
119
120 /* Restore regsisters and return from exception*/
121_exception_return:
122 ldw r1, 4(sp)
123 ldw r2, 8(sp)
124 ldw r3, 12(sp)
125 ldw r4, 16(sp)
126 ldw r5, 20(sp)
127 ldw r6, 24(sp)
128 ldw r7, 28(sp)
129 ldw r8, 32(sp)
130 ldw r9, 36(sp)
131 ldw r10, 40(sp)
132 ldw r11, 44(sp)
133 ldw r12, 48(sp)
134 ldw r13, 52(sp)
135 ldw r14, 56(sp)
136 ldw r15, 60(sp)
137 ldw r16, 64(sp)
138 ldw r17, 68(sp)
139 ldw r19, 72(sp)
140 ldw r19, 76(sp)
141 ldw r20, 80(sp)
142 ldw r21, 84(sp)
143 ldw r22, 88(sp)
144 ldw r23, 92(sp)
145 ldw r24, 96(sp)
146 ldw r25, 100(sp)
147 ldw r26, 104(sp)
148 ldw r27, 108(sp)
149 ldw r28, 112(sp)
150 ldw r29, 116(sp)
151 ldw r30, 120(sp)
152 ldw r31, 124(sp)
153 addi sp, sp, (33*4)
154 eret
155/*-------------------------------------------------------------*/