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roy zang87c4db02006-11-02 18:59:15 +08001/*****************************************************************************
2 * (C) Copyright 2003; Tundra Semiconductor Corp.
roy zangee311212006-12-01 11:47:36 +08003 *
roy zang87c4db02006-11-02 18:59:15 +08004 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *****************************************************************************/
19
20/*----------------------------------------------------------------------------
21 * FILENAME: tsi108_init.c
22 *
23 * Originator: Alex Bounine
24 *
25 * DESCRIPTION:
26 * Initialization code for the Tundra Tsi108 bridge chip
27 *---------------------------------------------------------------------------*/
28
29#include <common.h>
30#include <74xx_7xx.h>
31#include <config.h>
32#include <version.h>
33#include <asm/processor.h>
34#include <tsi108.h>
35
Wolfgang Denk1218abf2007-09-15 20:48:41 +020036DECLARE_GLOBAL_DATA_PTR;
37
roy zangee311212006-12-01 11:47:36 +080038extern void mpicInit (int verbose);
roy zang87c4db02006-11-02 18:59:15 +080039
40/*
41 * Configuration Options
42 */
43
44typedef struct {
45 ulong upper;
46 ulong lower;
47} PB2OCN_LUT_ENTRY;
48
49PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
50 /* 0 - 7 */
51 {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
52 {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
53 {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
54 {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
55 {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
56 {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
57 {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
58 {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
59
60 /* 8 - 15 */
61 {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
62 {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
63 {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
64 {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
65 {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
66 {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
67 {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
68 {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
69
70 /* 16 - 23 */
71 {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
72 {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
73 {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
74 {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
75 {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
76 {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
77 {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
78 {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
79 /* 24 - 31 */
80 {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
81 {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
82 {0x00000000, 0x00000201}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap) */
83 {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */
84
85 {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
86 {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
87 {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
88 {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
89};
90
91#ifdef CFG_CLK_SPREAD
92typedef struct {
93 ulong ctrl0;
94 ulong ctrl1;
95} PLL_CTRL_SET;
96
97/*
98 * Clock Generator SPLL0 initialization values
99 * PLL0 configuration table for various PB_CLKO freq.
100 * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
101 * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
102 */
103
104static PLL_CTRL_SET pll0_config[8] = {
105 {0x00000000, 0x00000000}, /* 0: bypass */
106 {0x00000000, 0x00000000}, /* 1: reserved */
107 {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */
108 {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */
109 {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */
110 {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */
111 {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
112 {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
113};
114#endif /* CFG_CLK_SPREAD */
115
116/*
117 * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
118 * (based on recommended Tsi108 reference clock 33MHz)
119 */
120static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
121
122/*
roy zangee311212006-12-01 11:47:36 +0800123 * get_board_bus_clk ()
roy zang87c4db02006-11-02 18:59:15 +0800124 *
125 * returns the bus clock in Hz.
126 */
roy zangee311212006-12-01 11:47:36 +0800127unsigned long get_board_bus_clk (void)
roy zang87c4db02006-11-02 18:59:15 +0800128{
129 ulong i;
130
131 /* Detect PB clock freq. */
132 i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
133 i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
134
135 return pb_clk_sel[i] * 1000000;
136}
137
138/*
roy zangee311212006-12-01 11:47:36 +0800139 * board_early_init_f ()
roy zang87c4db02006-11-02 18:59:15 +0800140 *
141 * board-specific initialization executed from flash
142 */
143
roy zangee311212006-12-01 11:47:36 +0800144int board_early_init_f (void)
roy zang87c4db02006-11-02 18:59:15 +0800145{
roy zang87c4db02006-11-02 18:59:15 +0800146 ulong i;
147
148 gd->mem_clk = 0;
roy zangee311212006-12-01 11:47:36 +0800149 i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
150 CG_PWRUP_STATUS);
roy zang9d27b3a2006-12-04 17:56:59 +0800151 i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
roy zang87c4db02006-11-02 18:59:15 +0800152 switch (i) {
roy zangee311212006-12-01 11:47:36 +0800153 case 0: /* external clock */
154 printf ("Using external clock\n");
roy zang87c4db02006-11-02 18:59:15 +0800155 break;
roy zangee311212006-12-01 11:47:36 +0800156 case 1: /* system clock */
roy zang87c4db02006-11-02 18:59:15 +0800157 gd->mem_clk = gd->bus_clk;
158 break;
roy zangee311212006-12-01 11:47:36 +0800159 case 4: /* 133 MHz */
160 case 5: /* 166 MHz */
161 case 6: /* 200 MHz */
roy zang87c4db02006-11-02 18:59:15 +0800162 gd->mem_clk = pb_clk_sel[i] * 1000000;
163 break;
164 default:
roy zangee311212006-12-01 11:47:36 +0800165 printf ("Invalid DDR2 clock setting\n");
roy zang87c4db02006-11-02 18:59:15 +0800166 return -1;
167 }
Wolfgang Denkbde63582008-07-11 22:56:11 +0200168 printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
169 printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
roy zang87c4db02006-11-02 18:59:15 +0800170 return 0;
171}
172
173/*
174 * board_early_init_r() - Tsi108 initialization function executed right after
175 * relocation. Contains code that cannot be executed from flash.
176 */
177
roy zangee311212006-12-01 11:47:36 +0800178int board_early_init_r (void)
roy zang87c4db02006-11-02 18:59:15 +0800179{
180 ulong temp, i;
181 ulong reg_val;
182 volatile ulong *reg_ptr;
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100183
roy zang87c4db02006-11-02 18:59:15 +0800184 reg_ptr =
roy zangee311212006-12-01 11:47:36 +0800185 (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
roy zang87c4db02006-11-02 18:59:15 +0800186
187 for (i = 0; i < 32; i++) {
188 *reg_ptr++ = 0x00000201; /* SWAP ENABLED */
189 *reg_ptr++ = 0x00;
190 }
191
roy zangee311212006-12-01 11:47:36 +0800192 __asm__ __volatile__ ("eieio");
193 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800194
195 /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
196
roy zangee311212006-12-01 11:47:36 +0800197 out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
198 0x80000001);
199 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800200
201 /* Make sure that OCN_BAR2 decoder is set (to allow following immediate
roy zangee311212006-12-01 11:47:36 +0800202 * read from SDRAM)
roy zang87c4db02006-11-02 18:59:15 +0800203 */
204
205 temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
roy zangee311212006-12-01 11:47:36 +0800206 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800207
208 /*
209 * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
210 * processor bus address space. Immediately after reset LUT and address
211 * translation are disabled for this BAR. Now we have to initialize LUT
212 * and switch from the BOOT mode to the normal operation mode.
roy zangee311212006-12-01 11:47:36 +0800213 *
roy zang87c4db02006-11-02 18:59:15 +0800214 * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
roy zangee311212006-12-01 11:47:36 +0800215 * and covers 512MB of address space. To allow larger aperture we also
roy zang87c4db02006-11-02 18:59:15 +0800216 * have to relocate register window of Tsi108
217 *
roy zangee311212006-12-01 11:47:36 +0800218 * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
roy zang87c4db02006-11-02 18:59:15 +0800219 * mode.
roy zangee311212006-12-01 11:47:36 +0800220 *
roy zang87c4db02006-11-02 18:59:15 +0800221 * initialize pointer to LUT associated with PB_OCN_BAR1
222 */
223 reg_ptr =
roy zangee311212006-12-01 11:47:36 +0800224 (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
roy zang87c4db02006-11-02 18:59:15 +0800225
226 for (i = 0; i < 32; i++) {
227 *reg_ptr++ = pb2ocn_lut1[i].lower;
228 *reg_ptr++ = pb2ocn_lut1[i].upper;
229 }
230
roy zangee311212006-12-01 11:47:36 +0800231 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800232
roy zang9d27b3a2006-12-04 17:56:59 +0800233 /* Base addresses for CS0, CS1, CS2, CS3 */
roy zang87c4db02006-11-02 18:59:15 +0800234
roy zangee311212006-12-01 11:47:36 +0800235 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
236 0x00000000);
237 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800238
roy zangee311212006-12-01 11:47:36 +0800239 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
240 0x00100000);
241 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800242
roy zangee311212006-12-01 11:47:36 +0800243 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
244 0x00200000);
245 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800246
roy zangee311212006-12-01 11:47:36 +0800247 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
248 0x00300000);
249 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800250
251 /* Masks for HLP banks */
252
roy zangee311212006-12-01 11:47:36 +0800253 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
254 0xFFF00000);
255 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800256
roy zangee311212006-12-01 11:47:36 +0800257 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
258 0xFFF00000);
259 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800260
roy zangee311212006-12-01 11:47:36 +0800261 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
262 0xFFF00000);
263 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800264
roy zangee311212006-12-01 11:47:36 +0800265 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
266 0xFFF00000);
267 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800268
269 /* Set CTRL0 values for banks */
270
roy zangee311212006-12-01 11:47:36 +0800271 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
272 0x7FFC44C2);
273 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800274
roy zangee311212006-12-01 11:47:36 +0800275 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
276 0x7FFC44C0);
277 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800278
roy zangee311212006-12-01 11:47:36 +0800279 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
280 0x7FFC44C0);
281 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800282
roy zangee311212006-12-01 11:47:36 +0800283 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
284 0x7FFC44C2);
285 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800286
287 /* Set banks to latched mode, enabled, and other default settings */
288
roy zangee311212006-12-01 11:47:36 +0800289 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
290 0x7C0F2000);
291 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800292
roy zangee311212006-12-01 11:47:36 +0800293 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
294 0x7C0F2000);
295 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800296
roy zangee311212006-12-01 11:47:36 +0800297 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
298 0x7C0F2000);
299 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800300
roy zangee311212006-12-01 11:47:36 +0800301 out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
302 0x7C0F2000);
303 __asm__ __volatile__ ("sync");
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100304
roy zang87c4db02006-11-02 18:59:15 +0800305 /*
306 * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
307 * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
308 */
roy zangee311212006-12-01 11:47:36 +0800309 out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
310 0xE0000011);
311 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800312
roy zangee311212006-12-01 11:47:36 +0800313 /* Make sure that OCN_BAR2 decoder is set (to allow following
314 * immediate read from SDRAM)
roy zang87c4db02006-11-02 18:59:15 +0800315 */
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100316
roy zang87c4db02006-11-02 18:59:15 +0800317 temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
roy zangee311212006-12-01 11:47:36 +0800318 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800319
320 /*
321 * SRI: At this point we have enabled the HLP banks. That means we can
322 * now read from the NVRAM and initialize the environment variables.
323 * We will over-ride the env_init called in board_init_f
324 * This is really a work-around because, the HLP bank 1
roy zangee311212006-12-01 11:47:36 +0800325 * where NVRAM resides is not visible during board_init_f
roy zang87c4db02006-11-02 18:59:15 +0800326 * (lib_ppc/board.c)
327 * Alternatively, we could use the I2C EEPROM at start-up to configure
328 * and enable all HLP banks and not just HLP 0 as is being done for
329 * Taiga Rev. 2.
330 */
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100331
roy zangee311212006-12-01 11:47:36 +0800332 env_init ();
roy zang87c4db02006-11-02 18:59:15 +0800333
334#ifndef DISABLE_PBM
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100335
roy zang87c4db02006-11-02 18:59:15 +0800336 /*
roy zangee311212006-12-01 11:47:36 +0800337 * For IBM processors we have to set Address-Only commands generated
roy zang87c4db02006-11-02 18:59:15 +0800338 * by PBM that are different from ones set after reset.
339 */
340
roy zangee311212006-12-01 11:47:36 +0800341 temp = get_cpu_type ();
roy zang87c4db02006-11-02 18:59:15 +0800342
roy zangee311212006-12-01 11:47:36 +0800343 if ((CPU_750FX == temp) || (CPU_750GX == temp))
344 out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
345 0x00009955);
roy zang87c4db02006-11-02 18:59:15 +0800346#endif /* DISABLE_PBM */
347
348#ifdef CONFIG_PCI
349 /*
350 * Initialize PCI/X block
351 */
352
353 /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
roy zangee311212006-12-01 11:47:36 +0800354 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
355 PCI_PFAB_BAR0_UPPER, 0);
356 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800357
roy zangee311212006-12-01 11:47:36 +0800358 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
359 0xFB000001);
360 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800361
362 /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
363
roy zangee311212006-12-01 11:47:36 +0800364 temp = in32(CFG_TSI108_CSR_BASE +
365 TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
roy zang87c4db02006-11-02 18:59:15 +0800366
367 temp &= ~0xFF00; /* Clear the BUS_NUM field */
368
roy zangee311212006-12-01 11:47:36 +0800369 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
370 temp);
roy zang87c4db02006-11-02 18:59:15 +0800371
372 /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
373
roy zangee311212006-12-01 11:47:36 +0800374 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
375 0);
376 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800377
378 /* This register is on the PCI side to interpret the address it receives
roy zangee311212006-12-01 11:47:36 +0800379 * and maps it as a IO address.
roy zang87c4db02006-11-02 18:59:15 +0800380 */
381
roy zangee311212006-12-01 11:47:36 +0800382 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
383 0xFA000001);
384 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800385
386 /*
387 * Map PCI/X Memory Space
388 *
roy zangee311212006-12-01 11:47:36 +0800389 * Transactions directed from OCM to PCI Memory Space are directed
roy zang87c4db02006-11-02 18:59:15 +0800390 * from PB to PCI
391 * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
392 * If address remapping is required the corresponding PCI_PFAB_MEM32
393 * and PCI_PFAB_PFMx register groups have to be configured.
394 *
395 * Map the path from the PCI/X bus into the system memory
396 *
roy zangee311212006-12-01 11:47:36 +0800397 * The memory mapped window assotiated with PCI P2O_BAR2 provides
roy zang87c4db02006-11-02 18:59:15 +0800398 * access to the system memory without address remapping.
399 * All system memory is opened for accesses initiated by PCI/X bus
400 * masters.
401 *
402 * Initialize LUT associated with PCI P2O_BAR2
403 *
404 * set pointer to LUT associated with PCI P2O_BAR2
405 */
406
407 reg_ptr =
roy zangee311212006-12-01 11:47:36 +0800408 (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
roy zang87c4db02006-11-02 18:59:15 +0800409
410#ifdef DISABLE_PBM
411
roy zangee311212006-12-01 11:47:36 +0800412 /* In case when PBM is disabled (no HW supported cache snoopng on PB)
413 * P2O_BAR2 is directly mapped into the system memory without address
414 * translation.
roy zang87c4db02006-11-02 18:59:15 +0800415 */
416
417 reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */
418
419 for (i = 0; i < 32; i++) {
420 *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
421 *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */
422 }
423
424 /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
425 reg_val = 0x00007500;
426#else
427
428 reg_val = 0x00000002; /* Destination port = PBM */
429
430 for (i = 0; i < 32; i++) {
431 *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
432/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
433 *reg_ptr++ = 0x40000000;
434/* offset = 16MB, address translation is enabled to allow byte swapping */
435 reg_val += 0x01000000;
436 }
437
438/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
439 reg_val = 0x00007100;
440#endif
441
roy zangee311212006-12-01 11:47:36 +0800442 __asm__ __volatile__ ("eieio");
443 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800444
roy zangee311212006-12-01 11:47:36 +0800445 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
446 reg_val);
447 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800448
roy zangee311212006-12-01 11:47:36 +0800449 /* Set 64-bit PCI bus address for system memory
450 * ( 0 is the best choice for easy mapping)
roy zang87c4db02006-11-02 18:59:15 +0800451 */
452
roy zangee311212006-12-01 11:47:36 +0800453 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
454 0x00000000);
455 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
456 0x00000000);
457 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800458
459#ifndef DISABLE_PBM
460 /*
roy zangee311212006-12-01 11:47:36 +0800461 * The memory mapped window assotiated with PCI P2O_BAR3 provides
462 * access to the system memory using SDRAM OCN port and address
463 * translation. This is alternative way to access SDRAM from PCI
roy zang87c4db02006-11-02 18:59:15 +0800464 * required for Tsi108 emulation testing.
roy zangee311212006-12-01 11:47:36 +0800465 * All system memory is opened for accesses initiated by
roy zang87c4db02006-11-02 18:59:15 +0800466 * PCI/X bus masters.
467 *
468 * Initialize LUT associated with PCI P2O_BAR3
469 *
470 * set pointer to LUT associated with PCI P2O_BAR3
471 */
472 reg_ptr =
roy zangee311212006-12-01 11:47:36 +0800473 (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
roy zang87c4db02006-11-02 18:59:15 +0800474
475 reg_val = 0x00000004; /* Destination port = SDC */
476
477 for (i = 0; i < 32; i++) {
478 *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100479
roy zang87c4db02006-11-02 18:59:15 +0800480/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100481 *reg_ptr++ = 0;
482
roy zang87c4db02006-11-02 18:59:15 +0800483/* offset = 16MB, address translation is enabled to allow byte swapping */
484 reg_val += 0x01000000;
485 }
486
roy zangee311212006-12-01 11:47:36 +0800487 __asm__ __volatile__ ("eieio");
488 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800489
490 /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
491
492 reg_val =
roy zangee311212006-12-01 11:47:36 +0800493 in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
roy zang87c4db02006-11-02 18:59:15 +0800494 PCI_P2O_PAGE_SIZES);
495 reg_val &= ~0x00FF;
496 reg_val |= 0x0071;
roy zangee311212006-12-01 11:47:36 +0800497 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
498 reg_val);
499 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800500
501 /* Set 64-bit base PCI bus address for window (0x20000000) */
502
roy zangee311212006-12-01 11:47:36 +0800503 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
504 0x00000000);
505 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
506 0x20000000);
507 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800508
509#endif /* !DISABLE_PBM */
510
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100511#ifdef ENABLE_PCI_CSR_BAR
roy zang87c4db02006-11-02 18:59:15 +0800512 /* open if required access to Tsi108 CSRs from the PCI/X bus */
513 /* enable BAR0 on the PCI/X bus */
roy zangee311212006-12-01 11:47:36 +0800514 reg_val = in32(CFG_TSI108_CSR_BASE +
515 TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
roy zang87c4db02006-11-02 18:59:15 +0800516 reg_val |= 0x02;
roy zangee311212006-12-01 11:47:36 +0800517 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
518 reg_val);
519 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800520
roy zangee311212006-12-01 11:47:36 +0800521 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
522 0x00000000);
523 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
524 CFG_TSI108_CSR_BASE);
525 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800526
527#endif
528
529 /*
530 * Finally enable PCI/X Bus Master and Memory Space access
531 */
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100532
roy zang87c4db02006-11-02 18:59:15 +0800533 reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
534 reg_val |= 0x06;
roy zangee311212006-12-01 11:47:36 +0800535 out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
536 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800537
538#endif /* CONFIG_PCI */
539
540 /*
541 * Initialize MPIC outputs (interrupt pins):
542 * Interrupt routing on the Grendel Emul. Board:
roy zangee311212006-12-01 11:47:36 +0800543 * PB_INT[0] -> INT (CPU0)
544 * PB_INT[1] -> INT (CPU1)
545 * PB_INT[2] -> MCP (CPU0)
546 * PB_INT[3] -> MCP (CPU1)
roy zang87c4db02006-11-02 18:59:15 +0800547 * Set interrupt controller outputs as Level_Sensitive/Active_Low
548 */
roy zangee311212006-12-01 11:47:36 +0800549 out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
550 out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
551 out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
552 out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
553 __asm__ __volatile__ ("sync");
roy zang87c4db02006-11-02 18:59:15 +0800554
555 /*
556 * Ensure that Machine Check exception is enabled
557 * We need it to support PCI Bus probing (configuration reads)
558 */
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100559
roy zangee311212006-12-01 11:47:36 +0800560 reg_val = mfmsr ();
roy zang87c4db02006-11-02 18:59:15 +0800561 mtmsr(reg_val | MSR_ME);
562
563 return 0;
564}
565
566/*
567 * Needed to print out L2 cache info
568 * used in the misc_init_r function
569 */
570
roy zangee311212006-12-01 11:47:36 +0800571unsigned long get_l2cr (void)
roy zang87c4db02006-11-02 18:59:15 +0800572{
573 unsigned long l2controlreg;
574 asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
575 return l2controlreg;
576}
577
578/*
579 * misc_init_r()
580 *
581 * various things to do after relocation
582 *
583 */
584
roy zangee311212006-12-01 11:47:36 +0800585int misc_init_r (void)
roy zang87c4db02006-11-02 18:59:15 +0800586{
roy zang87c4db02006-11-02 18:59:15 +0800587#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
588 ulong i;
589
590 /* Ensure that Spread-Spectrum is disabled */
roy zangee311212006-12-01 11:47:36 +0800591 out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
592 out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
roy zang87c4db02006-11-02 18:59:15 +0800593
594 /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
595 * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
596 */
597
roy zangee311212006-12-01 11:47:36 +0800598 out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
599 0x002e0044); /* D = 0.25% */
600 out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
601 0x00000039); /* BWADJ */
roy zang87c4db02006-11-02 18:59:15 +0800602
603 /* Initialize PLL0: CG_PB_CLKO */
604 /* Detect PB clock freq. */
605 i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
606 i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
607
roy zangee311212006-12-01 11:47:36 +0800608 out32 (CFG_TSI108_CSR_BASE +
609 TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
610 out32 (CFG_TSI108_CSR_BASE +
611 TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
roy zang87c4db02006-11-02 18:59:15 +0800612
613 /* Wait and set SSEN for both PLL0 and 1 */
roy zangee311212006-12-01 11:47:36 +0800614 udelay (1000);
615 out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
616 0x802e0044); /* D=0.25% */
617 out32 (CFG_TSI108_CSR_BASE +
618 TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200619 0x80000000 | pll0_config[i].ctrl0);
roy zang87c4db02006-11-02 18:59:15 +0800620#endif /* CFG_CLK_SPREAD */
621
622#ifdef CFG_L2
roy zangee311212006-12-01 11:47:36 +0800623 l2cache_enable ();
roy zang87c4db02006-11-02 18:59:15 +0800624#endif
Wolfgang Denkbde63582008-07-11 22:56:11 +0200625 printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000);
626 printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
roy zang87c4db02006-11-02 18:59:15 +0800627
628 /*
roy zangee311212006-12-01 11:47:36 +0800629 * All the information needed to print the cache details is avaiblable
630 * at this point i.e. above call to l2cache_enable is the very last
631 * thing done with regards to enabling diabling the cache.
roy zang87c4db02006-11-02 18:59:15 +0800632 * So this seems like a good place to print all this information
633 */
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100634
roy zangee311212006-12-01 11:47:36 +0800635 printf ("CACHE: ");
roy zang87c4db02006-11-02 18:59:15 +0800636 switch (get_cpu_type()) {
637 case CPU_7447A:
roy zangee311212006-12-01 11:47:36 +0800638 printf ("L1 Instruction cache - 32KB 8-way");
639 (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
640 printf (" DISABLED\n");
641 printf ("L1 Data cache - 32KB 8-way");
642 (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
643 printf (" DISABLED\n");
644 printf ("Unified L2 cache - 512KB 8-way");
645 (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
646 printf (" DISABLED\n");
647 printf ("\n");
roy zang87c4db02006-11-02 18:59:15 +0800648 break;
649
650 case CPU_7448:
roy zangee311212006-12-01 11:47:36 +0800651 printf ("L1 Instruction cache - 32KB 8-way");
652 (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
653 printf (" DISABLED\n");
654 printf ("L1 Data cache - 32KB 8-way");
655 (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
656 printf (" DISABLED\n");
657 printf ("Unified L2 cache - 1MB 8-way");
658 (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
659 printf (" DISABLED\n");
roy zang87c4db02006-11-02 18:59:15 +0800660 break;
661 default:
662 break;
663 }
664 return 0;
665}