blob: 819e456e459d14f2cbef8105ac6ac608d7cbcfa4 [file] [log] [blame]
Wolfgang Denk53dd6ce2006-07-21 11:29:20 +02001/*
2 * (C) Copyright 2005
3 * Sangmoon Kim, dogoil@etinsys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_MPC824X 1
28#define CONFIG_MPC8245 1
29#define CONFIG_KVME080 1
30
31#define CONFIG_CONS_INDEX 1
32
33#define CONFIG_BAUDRATE 115200
34
35#define CONFIG_BOOTDELAY 5
36
37#define CONFIG_IPADDR 192.168.0.2
38#define CONFIG_NETMASK 255.255.255.0
39#define CONFIG_SERVERIP 192.168.0.1
40
41#define CONFIG_BOOTARGS \
42 "console=ttyS0,115200 " \
43 "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
44 "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
45 "kvme080:eth0:none " \
46 "mtdparts=phys_mapped_flash:12m(root),-(kernel)"
47
48#define CONFIG_BOOTCOMMAND \
49 "tftp 800000 kvme080/uImage; " \
50 "bootm 800000"
51
52#define CONFIG_LOADADDR 800000
53
54#define CONFIG_BOARD_EARLY_INIT_F
55#define CONFIG_BOARD_EARLY_INIT_R
56#define CONFIG_MISC_INIT_R
57
58#define CONFIG_LOADS_ECHO 1
59#undef CFG_LOADS_BAUD_CHANGE
60
61#undef CONFIG_WATCHDOG
62
Jon Loeliger2fd90ce2007-07-09 21:48:26 -050063/*
64 * BOOTP options
65 */
66#define CONFIG_BOOTP_SUBNETMASK
67#define CONFIG_BOOTP_GATEWAY
68#define CONFIG_BOOTP_HOSTNAME
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_BOOTFILESIZE
71
Wolfgang Denk53dd6ce2006-07-21 11:29:20 +020072
73#define CONFIG_MAC_PARTITION
74#define CONFIG_DOS_PARTITION
75
76#define CONFIG_RTC_DS164x
77
Jon Loeligerbc234c12007-07-04 22:32:51 -050078
79/*
80 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83
84#define CONFIG_CMD_ASKENV
85#define CONFIG_CMD_CACHE
86#define CONFIG_CMD_DATE
87#define CONFIG_CMD_DHCP
88#define CONFIG_CMD_DIAG
89#define CONFIG_CMD_EEPROM
90#define CONFIG_CMD_ELF
91#define CONFIG_CMD_I2C
92#define CONFIG_CMD_JFFS2
93#define CONFIG_CMD_NFS
94#define CONFIG_CMD_PCI
95#define CONFIG_CMD_PING
96#define CONFIG_CMD_SDRAM
97#define CONFIG_CMD_SNTP
98
Wolfgang Denk53dd6ce2006-07-21 11:29:20 +020099
100#define CONFIG_NETCONSOLE
101
Wolfgang Denk53dd6ce2006-07-21 11:29:20 +0200102#define CFG_LONGHELP
103#define CFG_PROMPT "=> "
104#define CFG_CBSIZE 256
105#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
106#define CFG_MAXARGS 16
107#define CFG_BARGSIZE CFG_CBSIZE
108
109#define CFG_MEMTEST_START 0x00400000
110#define CFG_MEMTEST_END 0x07C00000
111
112#define CFG_LOAD_ADDR 0x00100000
113#define CFG_HZ 1000
114
115#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
116
117#define CFG_INIT_RAM_ADDR 0x40000000
118#define CFG_INIT_RAM_END 0x1000
119#define CFG_GBL_DATA_SIZE 128
120#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
121
122#define CFG_SDRAM_BASE 0x00000000
123#define CFG_FLASH_BASE 0x7C000000
124#define CFG_EUMB_ADDR 0xFC000000
125#define CFG_NVRAM_BASE_ADDR 0xFF000000
126#define CFG_NS16550_COM1 0xFF080000
127#define CFG_NS16550_COM2 0xFF080010
128#define CFG_NS16550_COM3 0xFF080020
129#define CFG_NS16550_COM4 0xFF080030
130#define CFG_RESET_ADDRESS 0xFFF00100
131
132#define CFG_MAX_RAM_SIZE 0x20000000
133#define CFG_FLASH_SIZE (16 * 1024 * 1024)
134#define CFG_NVRAM_SIZE 0x7FFF8
135
136#define CONFIG_VERY_BIG_RAM
137
138#define CFG_MONITOR_LEN 0x00040000
139#define CFG_MONITOR_BASE TEXT_BASE
140#define CFG_MALLOC_LEN (512 << 10)
141
142#define CFG_BOOTMAPSZ (8 << 20)
143
144#define CFG_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200145#define CONFIG_FLASH_CFI_DRIVER
Wolfgang Denk53dd6ce2006-07-21 11:29:20 +0200146#define CFG_FLASH_USE_BUFFER_WRITE
147#define CFG_FLASH_PROTECTION
148#define CFG_FLASH_EMPTY_INFO
149#define CFG_FLASH_PROTECT_CLEAR
150
151#define CFG_MAX_FLASH_BANKS 1
152#define CFG_MAX_FLASH_SECT 256
153
154#define CFG_FLASH_ERASE_TOUT 120000
155#define CFG_FLASH_WRITE_TOUT 500
156
157#define CFG_JFFS2_FIRST_BANK 0
158#define CFG_JFFS2_NUM_BANKS 1
159
160#define CFG_ENV_IS_IN_NVRAM 1
161#define CONFIG_ENV_OVERWRITE 1
162#define CFG_NVRAM_ACCESS_ROUTINE
163#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR
164#define CFG_ENV_SIZE 0x400
165#define CFG_ENV_OFFSET 0
166
167#define CFG_NS16550
168#define CFG_NS16550_SERIAL
169#define CFG_NS16550_REG_SIZE 1
170#define CFG_NS16550_CLK 14745600
171
172#define CONFIG_PCI
173#define CONFIG_PCI_PNP
174
175#define CONFIG_NET_MULTI
176#define CONFIG_EEPRO100
177#define CONFIG_EEPRO100_SROM_WRITE
178
179#define CFG_RX_ETH_BUFFER 8
180
181#define CONFIG_HARD_I2C 1
182#define CFG_I2C_SPEED 400000
183#define CFG_I2C_SLAVE 0x7F
184
185#define CFG_I2C_EEPROM_ADDR 0x57
186#define CFG_I2C_EEPROM_ADDR_LEN 1
187#define CFG_EEPROM_PAGE_WRITE_BITS 3
188#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
189
190#define CONFIG_SYS_CLK_FREQ 33333333
191
192#define CFG_CACHELINE_SIZE 32
Jon Loeligerbc234c12007-07-04 22:32:51 -0500193#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk53dd6ce2006-07-21 11:29:20 +0200194# define CFG_CACHELINE_SHIFT 5
195#endif
196
197#define CFG_DLL_EXTEND 0x00
198#define CFG_PCI_HOLD_DEL 0x20
199
200#define CFG_ROMNAL 15
201#define CFG_ROMFAL 31
202
203#define CFG_REFINT 430
204
205#define CFG_DBUS_SIZE2 1
206
207#define CFG_BSTOPRE 121
208#define CFG_REFREC 8
209#define CFG_RDLAT 4
210#define CFG_PRETOACT 3
211#define CFG_ACTTOPRE 5
212#define CFG_ACTORW 3
213#define CFG_SDMODE_CAS_LAT 3
214#define CFG_SDMODE_WRAP 0
215
216#define CFG_REGISTERD_TYPE_BUFFER 1
217#define CFG_EXTROM 1
218#define CFG_REGDIMM 0
219
220#define CFG_BANK0_START 0x00000000
221#define CFG_BANK0_END (0x4000000 - 1)
222#define CFG_BANK0_ENABLE 1
223#define CFG_BANK1_START 0x04000000
224#define CFG_BANK1_END (0x8000000 - 1)
225#define CFG_BANK1_ENABLE 1
226#define CFG_BANK2_START 0x3ff00000
227#define CFG_BANK2_END 0x3fffffff
228#define CFG_BANK2_ENABLE 0
229#define CFG_BANK3_START 0x3ff00000
230#define CFG_BANK3_END 0x3fffffff
231#define CFG_BANK3_ENABLE 0
232#define CFG_BANK4_START 0x00000000
233#define CFG_BANK4_END 0x00000000
234#define CFG_BANK4_ENABLE 0
235#define CFG_BANK5_START 0x00000000
236#define CFG_BANK5_END 0x00000000
237#define CFG_BANK5_ENABLE 0
238#define CFG_BANK6_START 0x00000000
239#define CFG_BANK6_END 0x00000000
240#define CFG_BANK6_ENABLE 0
241#define CFG_BANK7_START 0x00000000
242#define CFG_BANK7_END 0x00000000
243#define CFG_BANK7_ENABLE 0
244
245#define CFG_BANK_ENABLE 0x03
246
247#define CFG_ODCR 0x75
248#define CFG_PGMAX 0x32
249
250#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
251#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
252
253#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
254#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
255
256#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
257#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
258
259#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
260#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
261
262#define CFG_DBAT0L CFG_IBAT0L
263#define CFG_DBAT0U CFG_IBAT0U
264#define CFG_DBAT1L CFG_IBAT1L
265#define CFG_DBAT1U CFG_IBAT1U
266#define CFG_DBAT2L CFG_IBAT2L
267#define CFG_DBAT2U CFG_IBAT2U
268#define CFG_DBAT3L CFG_IBAT3L
269#define CFG_DBAT3U CFG_IBAT3U
270
271#define BOOTFLAG_COLD 0x01
272#define BOOTFLAG_WARM 0x02
273
274#endif /* __CONFIG_H */