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wdenk0e6d7982004-03-14 00:07:33 +00001/*
2 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
3 *
Stefan Roese8a316c92005-08-01 16:49:12 +02004 * (C) Copyright 2005
5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 *
wdenk0e6d7982004-03-14 00:07:33 +00007 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/************************************************************************
wdenk42dfe7a2004-03-14 22:25:36 +000027 * 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com>
wdenk0e6d7982004-03-14 00:07:33 +000028 * Adapted to current Das U-Boot source
29 ***********************************************************************/
30
31
32/************************************************************************
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020033 * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
wdenk0e6d7982004-03-14 00:07:33 +000034 ***********************************************************************/
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*-----------------------------------------------------------------------
40 * High Level Configuration Options
41 *----------------------------------------------------------------------*/
42#define CONFIG_OCOTEA 1 /* Board is ebony */
Stefan Roese846b0dd2005-08-08 12:42:22 +020043#define CONFIG_440GX 1 /* Specifc GX support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020044#define CONFIG_440 1 /* ... PPC440 family */
wdenk0e6d7982004-03-14 00:07:33 +000045#define CONFIG_4xx 1 /* ... PPC4xx family */
46#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
wdenk0e6d7982004-03-14 00:07:33 +000047#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
48
Stefan Roese72675dc2008-06-06 15:55:21 +020049/*
50 * Include common defines/options for all AMCC eval boards
51 */
52#define CONFIG_HOSTNAME ocotea
53#include "amcc-common.h"
54
wdenk0e6d7982004-03-14 00:07:33 +000055/*-----------------------------------------------------------------------
56 * Base addresses -- Note these are effective addresses where the
57 * actual resources get mapped (not physical addresses)
58 *----------------------------------------------------------------------*/
wdenk0e6d7982004-03-14 00:07:33 +000059#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
wdenk0e6d7982004-03-14 00:07:33 +000060#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
61#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
62#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
63#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
64
65#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
66#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
67
68/*-----------------------------------------------------------------------
69 * Initial RAM & stack pointer (placed in internal SRAM)
70 *----------------------------------------------------------------------*/
71#define CFG_TEMP_STACK_OCM 1
72#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
73#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
74#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
75#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
76
77#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenk42dfe7a2004-03-14 22:25:36 +000078#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
79#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
wdenk0e6d7982004-03-14 00:07:33 +000080
wdenk0e6d7982004-03-14 00:07:33 +000081/*-----------------------------------------------------------------------
82 * Serial Port
83 *----------------------------------------------------------------------*/
84#undef CONFIG_SERIAL_SOFTWARE_FIFO
85#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
wdenk0e6d7982004-03-14 00:07:33 +000086
87/*-----------------------------------------------------------------------
Stefan Roese8a316c92005-08-01 16:49:12 +020088 * Environment
89 *----------------------------------------------------------------------*/
90/*
91 * Define here the location of the environment variables (FLASH or NVRAM).
92 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
93 * supported for backward compatibility.
94 */
95#if 1
96#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
97#else
98#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
99#endif
100
101
102/*-----------------------------------------------------------------------
wdenk0e6d7982004-03-14 00:07:33 +0000103 * NVRAM/RTC
104 *
105 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
106 * The DS1743 code assumes this condition (i.e. -- it assumes the base
107 * address for the RTC registers is:
108 *
109 * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
110 *
111 *----------------------------------------------------------------------*/
112#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
113#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
114
Stefan Roese8a316c92005-08-01 16:49:12 +0200115#ifdef CFG_ENV_IS_IN_NVRAM
116#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
117#define CFG_ENV_ADDR \
118 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
119#endif /* CFG_ENV_IS_IN_NVRAM */
120
wdenk0e6d7982004-03-14 00:07:33 +0000121/*-----------------------------------------------------------------------
122 * FLASH related
123 *----------------------------------------------------------------------*/
124#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
125#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
126
127#undef CFG_FLASH_CHECKSUM
128#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
129#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
130
Stefan Roese8a316c92005-08-01 16:49:12 +0200131#define CFG_FLASH_ADDR0 0x5555
132#define CFG_FLASH_ADDR1 0x2aaa
133#define CFG_FLASH_WORD_SIZE unsigned char
134
135#ifdef CFG_ENV_IS_IN_FLASH
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200136#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Stefan Roese8a316c92005-08-01 16:49:12 +0200137#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
138#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
139
140/* Address and size of Redundant Environment Sector */
141#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
142#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
143#endif /* CFG_ENV_IS_IN_FLASH */
144
wdenk0e6d7982004-03-14 00:07:33 +0000145/*-----------------------------------------------------------------------
146 * DDR SDRAM
147 *----------------------------------------------------------------------*/
Stefan Roesefa1aef12007-03-07 16:43:00 +0100148#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
wdenk42dfe7a2004-03-14 22:25:36 +0000149#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
Stefan Roesefa1aef12007-03-07 16:43:00 +0100150#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
wdenk0e6d7982004-03-14 00:07:33 +0000151
152/*-----------------------------------------------------------------------
153 * I2C
154 *----------------------------------------------------------------------*/
wdenk0e6d7982004-03-14 00:07:33 +0000155#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
Stefan Roese4f92ed52006-08-07 14:33:32 +0200156
157#define CFG_I2C_MULTI_EEPROMS
158#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
159#define CFG_I2C_EEPROM_ADDR_LEN 1
160#define CFG_EEPROM_PAGE_WRITE_ENABLE
161#define CFG_EEPROM_PAGE_WRITE_BITS 3
162#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenk0e6d7982004-03-14 00:07:33 +0000163
Stefan Roese72675dc2008-06-06 15:55:21 +0200164/*
165 * Default environment variables
166 */
Stefan Roese8a316c92005-08-01 16:49:12 +0200167#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese72675dc2008-06-06 15:55:21 +0200168 CONFIG_AMCC_DEF_ENV \
169 CONFIG_AMCC_DEF_ENV_PPC \
170 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese8a316c92005-08-01 16:49:12 +0200171 "kernel_addr=fff00000\0" \
172 "ramdisk_addr=fff10000\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200173 ""
wdenk0e6d7982004-03-14 00:07:33 +0000174
wdenk0e6d7982004-03-14 00:07:33 +0000175#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
wdenk42dfe7a2004-03-14 22:25:36 +0000176#define CONFIG_PHY1_ADDR 2
177#define CONFIG_PHY2_ADDR 0x10
178#define CONFIG_PHY3_ADDR 0x18
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200179#define CONFIG_HAS_ETH0
180#define CONFIG_HAS_ETH1
181#define CONFIG_HAS_ETH2
182#define CONFIG_HAS_ETH3
wdenk42dfe7a2004-03-14 22:25:36 +0000183#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
wdenk6fb6af62004-03-23 23:20:24 +0000184#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200185#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
186#define CONFIG_PHY_RESET_DELAY 1000
wdenk0e6d7982004-03-14 00:07:33 +0000187
Jon Loeligera5cb2302007-07-04 22:33:13 -0500188/*
Stefan Roese72675dc2008-06-06 15:55:21 +0200189 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500190 */
Jon Loeligera5cb2302007-07-04 22:33:13 -0500191#define CONFIG_CMD_DATE
Jon Loeligera5cb2302007-07-04 22:33:13 -0500192#define CONFIG_CMD_PCI
Jon Loeligera5cb2302007-07-04 22:33:13 -0500193#define CONFIG_CMD_SDRAM
194#define CONFIG_CMD_SNTP
195
wdenk0e6d7982004-03-14 00:07:33 +0000196/*-----------------------------------------------------------------------
197 * PCI stuff
198 *-----------------------------------------------------------------------
199 */
200/* General PCI */
Stefan Roese8a316c92005-08-01 16:49:12 +0200201#define CONFIG_PCI /* include pci support */
202#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk42dfe7a2004-03-14 22:25:36 +0000203#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
204#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
wdenk0e6d7982004-03-14 00:07:33 +0000205
206/* Board-specific PCI */
Stefan Roese8a316c92005-08-01 16:49:12 +0200207#define CFG_PCI_TARGET_INIT /* let board init pci target */
wdenk0e6d7982004-03-14 00:07:33 +0000208
Stefan Roese8a316c92005-08-01 16:49:12 +0200209#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
wdenk42dfe7a2004-03-14 22:25:36 +0000210#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
wdenk0e6d7982004-03-14 00:07:33 +0000211
wdenk0e6d7982004-03-14 00:07:33 +0000212#endif /* __CONFIG_H */