blob: f69eec18d8657b01e19f686d623dcafc7cdfeb9e [file] [log] [blame]
Abel Vesa67f165d2019-02-01 16:40:16 +00001// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2016 Freescale Semiconductor, Inc.
4
5/dts-v1/;
6
7#include "imx6qp.dtsi"
8#include "imx6qdl-sabresd.dtsi"
9
10/ {
11 model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
12 compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
13};
14
15&reg_arm {
16 vin-supply = <&sw2_reg>;
17};
18
19&iomuxc {
20 imx6qdl-sabresd {
21 pinctrl_usdhc2: usdhc2grp {
22 fsl,pins = <
23 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
24 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
25 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
26 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
27 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
28 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
29 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
30 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
31 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
32 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
33 >;
34 };
35
36 pinctrl_usdhc3: usdhc3grp {
37 fsl,pins = <
38 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
39 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
40 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
41 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
42 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
43 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
44 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
45 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
46 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
47 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
48 >;
49 };
50 };
51};
52
Marcel Ziswiler175a8742022-10-22 23:59:38 +020053&vgen3_reg {
54 regulator-always-on;
55};
56
Abel Vesa67f165d2019-02-01 16:40:16 +000057&pcie {
Marcel Ziswiler175a8742022-10-22 23:59:38 +020058 status = "okay";
59};
60
61&sata {
62 status = "okay";
Abel Vesa67f165d2019-02-01 16:40:16 +000063};