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stroeseb3182622003-09-12 08:41:56 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
Matthias Fuchsbd84ee42007-07-09 10:10:06 +020026#include <asm/io.h>
stroeseb3182622003-09-12 08:41:56 +000027#include <command.h>
28#include <malloc.h>
29
stroeseb3182622003-09-12 08:41:56 +000030
31#if 0
32#define FPGA_DEBUG
33#endif
34
Matthias Fuchsbd84ee42007-07-09 10:10:06 +020035DECLARE_GLOBAL_DATA_PTR;
36
stroeseb3182622003-09-12 08:41:56 +000037extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
stroese12537cc2004-12-16 18:39:03 +000038extern void lxt971_no_sleep(void);
stroeseb3182622003-09-12 08:41:56 +000039
40/* fpga configuration data - gzip compressed and generated by bin2c */
41const unsigned char fpgadata[] =
42{
43#include "fpgadata.c"
44};
45
46/*
47 * include common fpga code (for esd boards)
48 */
49#include "../common/fpga.c"
50
51
stroese12537cc2004-12-16 18:39:03 +000052/*
53 * include common auto-update code (for esd boards)
54 */
55#include "../common/auto_update.h"
56
57au_image_t au_image[] = {
58 {"plu405/preinst.img", 0, -1, AU_SCRIPT},
59 {"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 {"plu405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
stroese12537cc2004-12-16 18:39:03 +000061 {"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
62 {"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
63 {"plu405/postinst.img", 0, 0, AU_SCRIPT},
64};
65
66int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
67
68
stroeseb3182622003-09-12 08:41:56 +000069/* Prototypes */
wdenkeedcd072004-09-08 22:03:11 +000070int gunzip(void *, int, unsigned char *, unsigned long *);
stroeseb3182622003-09-12 08:41:56 +000071
72
wdenkc837dcb2004-01-20 23:12:12 +000073int board_early_init_f (void)
stroeseb3182622003-09-12 08:41:56 +000074{
75 /*
76 * IRQ 0-15 405GP internally generated; active high; level sensitive
77 * IRQ 16 405GP internally generated; active low; level sensitive
78 * IRQ 17-24 RESERVED
79 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
80 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
81 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
82 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
83 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
84 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
85 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
86 */
87 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
88 mtdcr(uicer, 0x00000000); /* disable all ints */
89 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
90 mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
91 mtdcr(uictr, 0x10000000); /* set int trigger levels */
92 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
93 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
94
95 /*
96 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
97 */
98 mtebc (epcr, 0xa8400000); /* ebc always driven */
99
100 return 0;
101}
102
103
stroeseb3182622003-09-12 08:41:56 +0000104int misc_init_f (void)
105{
106 return 0; /* dummy implementation */
107}
108
109
110int misc_init_r (void)
111{
Matthias Fuchsf6e0f1f2007-12-28 17:10:36 +0100112 unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
113 unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
stroeseb3182622003-09-12 08:41:56 +0000114 unsigned char *dst;
115 ulong len = sizeof(fpgadata);
116 int status;
117 int index;
118 int i;
119
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200120 /* adjust flash start and offset */
121 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
122 gd->bd->bi_flashoffset = 0;
123
stroeseb3182622003-09-12 08:41:56 +0000124 dst = malloc(CFG_FPGA_MAX_SIZE);
wdenkeedcd072004-09-08 22:03:11 +0000125 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
stroeseb3182622003-09-12 08:41:56 +0000126 printf ("GUNZIP ERROR - must RESET board to recover\n");
127 do_reset (NULL, 0, 0, NULL);
128 }
129
130 status = fpga_boot(dst, len);
131 if (status != 0) {
132 printf("\nFPGA: Booting failed ");
133 switch (status) {
134 case ERROR_FPGA_PRG_INIT_LOW:
135 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
136 break;
137 case ERROR_FPGA_PRG_INIT_HIGH:
138 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
139 break;
140 case ERROR_FPGA_PRG_DONE:
141 printf("(Timeout: DONE not high after programming FPGA)\n ");
142 break;
143 }
144
145 /* display infos on fpgaimage */
146 index = 15;
147 for (i=0; i<4; i++) {
148 len = dst[index];
149 printf("FPGA: %s\n", &(dst[index+1]));
150 index += len+3;
151 }
152 putc ('\n');
153 /* delayed reboot */
154 for (i=20; i>0; i--) {
155 printf("Rebooting in %2d seconds \r",i);
156 for (index=0;index<1000;index++)
157 udelay(1000);
158 }
159 putc ('\n');
160 do_reset(NULL, 0, 0, NULL);
161 }
162
163 puts("FPGA: ");
164
165 /* display infos on fpgaimage */
166 index = 15;
167 for (i=0; i<4; i++) {
168 len = dst[index];
169 printf("%s ", &(dst[index+1]));
170 index += len+3;
171 }
172 putc ('\n');
173
174 free(dst);
175
176 /*
177 * Reset FPGA via FPGA_DATA pin
178 */
179 SET_FPGA(FPGA_PRG | FPGA_CLK);
180 udelay(1000); /* wait 1ms */
181 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
182 udelay(1000); /* wait 1ms */
183
184 /*
185 * Reset external DUARTs
186 */
Matthias Fuchsf6e0f1f2007-12-28 17:10:36 +0100187 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
stroeseb3182622003-09-12 08:41:56 +0000188 udelay(10); /* wait 10us */
Matthias Fuchsf6e0f1f2007-12-28 17:10:36 +0100189 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
stroeseb3182622003-09-12 08:41:56 +0000190 udelay(1000); /* wait 1ms */
191
192 /*
Matthias Fuchsf6e0f1f2007-12-28 17:10:36 +0100193 * Set NAND-FLASH GPIO signals to default
194 */
195 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
196 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
197
198 /*
199 * Setup EEPROM write protection
200 */
201 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
202 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
203
204 /*
stroeseb3182622003-09-12 08:41:56 +0000205 * Enable interrupts in exar duart mcr[3]
206 */
Matthias Fuchsf6e0f1f2007-12-28 17:10:36 +0100207 out_8(duart0_mcr, 0x08);
208 out_8(duart1_mcr, 0x08);
stroeseb3182622003-09-12 08:41:56 +0000209
210 return (0);
211}
212
213
214/*
215 * Check Board Identity:
216 */
stroeseb3182622003-09-12 08:41:56 +0000217int checkboard (void)
218{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200219 char str[64];
stroeseb3182622003-09-12 08:41:56 +0000220 int i = getenv_r ("serial#", str, sizeof(str));
221
222 puts ("Board: ");
223
224 if (i == -1) {
225 puts ("### No HW ID - assuming PLU405");
226 } else {
227 puts(str);
228 }
229
230 putc ('\n');
stroeseb3182622003-09-12 08:41:56 +0000231 return 0;
232}
233
stroeseb3182622003-09-12 08:41:56 +0000234
235long int initdram (int board_type)
236{
237 unsigned long val;
238
239 mtdcr(memcfga, mem_mb0cf);
240 val = mfdcr(memcfgd);
241
stroeseb3182622003-09-12 08:41:56 +0000242 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
243}
244
stroeseb3182622003-09-12 08:41:56 +0000245
stroeseb3182622003-09-12 08:41:56 +0000246#ifdef CONFIG_IDE_RESET
247void ide_set_reset(int on)
248{
249 volatile unsigned short *fpga_mode =
250 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
251
252 /*
253 * Assert or deassert CompactFlash Reset Pin
254 */
255 if (on) { /* assert RESET */
256 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
257 } else { /* release RESET */
258 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
259 }
260}
261#endif /* CONFIG_IDE_RESET */
262
263
Matthias Fuchsf9fc6a52007-03-07 15:32:01 +0100264void reset_phy(void)
265{
266#ifdef CONFIG_LXT971_NO_SLEEP
267
268 /*
269 * Disable sleep mode in LXT971
270 */
271 lxt971_no_sleep();
272#endif
273}
Matthias Fuchsf6e0f1f2007-12-28 17:10:36 +0100274
275
276#if defined(CFG_EEPROM_WREN)
277/* Input: <dev_addr> I2C address of EEPROM device to enable.
278 * <state> -1: deliver current state
279 * 0: disable write
280 * 1: enable write
281 * Returns: -1: wrong device address
282 * 0: dis-/en- able done
283 * 0/1: current state if <state> was -1.
284 */
285int eeprom_write_enable (unsigned dev_addr, int state)
286{
287 if (CFG_I2C_EEPROM_ADDR != dev_addr) {
288 return -1;
289 } else {
290 switch (state) {
291 case 1:
292 /* Enable write access, clear bit GPIO0. */
293 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
294 state = 0;
295 break;
296 case 0:
297 /* Disable write access, set bit GPIO0. */
298 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
299 state = 0;
300 break;
301 default:
302 /* Read current status back. */
303 state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
304 break;
305 }
306 }
307 return state;
308}
309
310int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
311{
312 int query = argc == 1;
313 int state = 0;
314
315 if (query) {
316 /* Query write access state. */
317 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
318 if (state < 0) {
319 puts ("Query of write access state failed.\n");
320 } else {
321 printf ("Write access for device 0x%0x is %sabled.\n",
322 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
323 state = 0;
324 }
325 } else {
326 if ('0' == argv[1][0]) {
327 /* Disable write access. */
328 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
329 } else {
330 /* Enable write access. */
331 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
332 }
333 if (state < 0) {
334 puts ("Setup of write access state failed.\n");
335 }
336 }
337
338 return state;
339}
340
341U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
342 "eepwren - Enable / disable / query EEPROM write access\n",
343 NULL);
344#endif /* #if defined(CFG_EEPROM_WREN) */