blob: d073399606caf8616ac9b4f91059e12bebe8008b [file] [log] [blame]
Kumar Gala143b5182008-01-17 01:44:34 -06001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
30/* TLB for CCSRBAR (IMMR) */
Kumar Galaf69766e2008-01-30 14:55:14 -060031 SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
Kumar Gala143b5182008-01-17 01:44:34 -060032 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
33 0, 1, BOOKE_PAGESZ_1M, 1),
34
35/* TLB for Local Bus stuff, just map the whole 512M */
36/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
37
38 SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000,
39 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
40 0, 2, BOOKE_PAGESZ_256M, 1),
41
42 SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000,
43 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
44 0, 3, BOOKE_PAGESZ_256M, 1),
45
46#if !defined(CONFIG_SPD_EEPROM)
47 SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
48 MAS3_SX|MAS3_SW|MAS3_SR, 0,
49 0, 4, BOOKE_PAGESZ_256M, 1),
50
51 SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
52 MAS3_SX|MAS3_SW|MAS3_SR, 0,
53 0, 5, BOOKE_PAGESZ_256M, 1),
54#endif
55
56 SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
57 MAS3_SX|MAS3_SW|MAS3_SR, 0,
58 0, 6, BOOKE_PAGESZ_16K, 1),
59
60 SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS,
61 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
62 0, 7, BOOKE_PAGESZ_256M, 1),
63};
64
65int num_tlb_entries = ARRAY_SIZE(tlb_table);