blob: f33cd1eaed64a2a331acfedd7f3a76d27befb367 [file] [log] [blame]
Tom Rix8966eb42009-06-28 12:52:28 -05001/*
2 * Copyright (c) 2009 Wind River Systems, Inc.
3 * Tom Rix <Tom.Rix at windriver.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Tom Rix8966eb42009-06-28 12:52:28 -05006 *
7 * Derived from code on omapzoom, git://git.omapzoom.com/repo/u-boot.git
8 *
9 * Copyright (C) 2007-2009 Texas Instruments, Inc.
10 */
11
12#ifndef TWL4030_H
13#define TWL4030_H
14
15#include <common.h>
16#include <i2c.h>
17
18/* I2C chip addresses */
19
20/* USB */
21#define TWL4030_CHIP_USB 0x48
22/* AUD */
23#define TWL4030_CHIP_AUDIO_VOICE 0x49
24#define TWL4030_CHIP_GPIO 0x49
25#define TWL4030_CHIP_INTBR 0x49
26#define TWL4030_CHIP_PIH 0x49
27#define TWL4030_CHIP_TEST 0x49
28/* AUX */
29#define TWL4030_CHIP_KEYPAD 0x4a
30#define TWL4030_CHIP_MADC 0x4a
31#define TWL4030_CHIP_INTERRUPTS 0x4a
32#define TWL4030_CHIP_LED 0x4a
33#define TWL4030_CHIP_MAIN_CHARGE 0x4a
34#define TWL4030_CHIP_PRECHARGE 0x4a
35#define TWL4030_CHIP_PWM0 0x4a
36#define TWL4030_CHIP_PWM1 0x4a
37#define TWL4030_CHIP_PWMA 0x4a
38#define TWL4030_CHIP_PWMB 0x4a
39/* POWER */
40#define TWL4030_CHIP_BACKUP 0x4b
41#define TWL4030_CHIP_INT 0x4b
42#define TWL4030_CHIP_PM_MASTER 0x4b
43#define TWL4030_CHIP_PM_RECEIVER 0x4b
44#define TWL4030_CHIP_RTC 0x4b
45#define TWL4030_CHIP_SECURED_REG 0x4b
46
47/* Register base addresses */
48
49/* USB */
50#define TWL4030_BASEADD_USB 0x0000
51/* AUD */
52#define TWL4030_BASEADD_AUDIO_VOICE 0x0000
53#define TWL4030_BASEADD_GPIO 0x0098
54#define TWL4030_BASEADD_INTBR 0x0085
55#define TWL4030_BASEADD_PIH 0x0080
56#define TWL4030_BASEADD_TEST 0x004C
57/* AUX */
58#define TWL4030_BASEADD_INTERRUPTS 0x00B9
59#define TWL4030_BASEADD_LED 0x00EE
60#define TWL4030_BASEADD_MADC 0x0000
61#define TWL4030_BASEADD_MAIN_CHARGE 0x0074
62#define TWL4030_BASEADD_PRECHARGE 0x00AA
63#define TWL4030_BASEADD_PWM0 0x00F8
64#define TWL4030_BASEADD_PWM1 0x00FB
65#define TWL4030_BASEADD_PWMA 0x00EF
66#define TWL4030_BASEADD_PWMB 0x00F1
67#define TWL4030_BASEADD_KEYPAD 0x00D2
68/* POWER */
69#define TWL4030_BASEADD_BACKUP 0x0014
70#define TWL4030_BASEADD_INT 0x002E
71#define TWL4030_BASEADD_PM_MASTER 0x0036
72#define TWL4030_BASEADD_PM_RECIEVER 0x005B
73#define TWL4030_BASEADD_RTC 0x001C
74#define TWL4030_BASEADD_SECURED_REG 0x0000
75
76/*
77 * Power Management Master
78 */
79#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x36
80#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x37
81#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x38
82#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x39
83#define TWL4030_PM_MASTER_STS_BOOT 0x3A
84#define TWL4030_PM_MASTER_CFG_BOOT 0x3B
85#define TWL4030_PM_MASTER_SHUNDAN 0x3C
86#define TWL4030_PM_MASTER_BOOT_BCI 0x3D
87#define TWL4030_PM_MASTER_CFG_PWRANA1 0x3E
88#define TWL4030_PM_MASTER_CFG_PWRANA2 0x3F
89#define TWL4030_PM_MASTER_BGAP_TRIM 0x40
90#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x41
91#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x42
92#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x43
93#define TWL4030_PM_MASTER_PROTECT_KEY 0x44
94#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x45
95#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x46
96#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x47
97#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x48
98#define TWL4030_PM_MASTER_STS_P123_STATE 0x49
99#define TWL4030_PM_MASTER_PB_CFG 0x4A
100#define TWL4030_PM_MASTER_PB_WORD_MSB 0x4B
101#define TWL4030_PM_MASTER_PB_WORD_LSB 0x4C
102#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x52
103#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x53
104#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x54
105#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x55
106#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x56
107#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x57
108#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x58
109#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x59
110#define TWL4030_PM_MASTER_MEMORY_DATA 0x5A
111#define TWL4030_PM_MASTER_SC_CONFIG 0x5B
112#define TWL4030_PM_MASTER_SC_DETECT1 0x5C
113#define TWL4030_PM_MASTER_SC_DETECT2 0x5D
114#define TWL4030_PM_MASTER_WATCHDOG_CFG 0x5E
115#define TWL4030_PM_MASTER_IT_CHECK_CFG 0x5F
116#define TWL4030_PM_MASTER_VIBRATOR_CFG 0x60
117#define TWL4030_PM_MASTER_DCDC_GLOBAL_CFG 0x61
118#define TWL4030_PM_MASTER_VDD1_TRIM1 0x62
119#define TWL4030_PM_MASTER_VDD1_TRIM2 0x63
120#define TWL4030_PM_MASTER_VDD2_TRIM1 0x64
121#define TWL4030_PM_MASTER_VDD2_TRIM2 0x65
122#define TWL4030_PM_MASTER_VIO_TRIM1 0x66
123#define TWL4030_PM_MASTER_VIO_TRIM2 0x67
124#define TWL4030_PM_MASTER_MISC_CFG 0x68
125#define TWL4030_PM_MASTER_LS_TST_A 0x69
126#define TWL4030_PM_MASTER_LS_TST_B 0x6A
127#define TWL4030_PM_MASTER_LS_TST_C 0x6B
128#define TWL4030_PM_MASTER_LS_TST_D 0x6C
129#define TWL4030_PM_MASTER_BB_CFG 0x6D
130#define TWL4030_PM_MASTER_MISC_TST 0x6E
131#define TWL4030_PM_MASTER_TRIM1 0x6F
132/* P[1-3]_SW_EVENTS */
133#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6)
134#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5)
135#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4)
136#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3)
137#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2)
138#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1)
139#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
140
Pali Rohár318e70e2012-10-19 02:00:06 +0000141/* Power bus message definitions */
142
143/* The TWL4030/5030 splits its power-management resources (the various
144 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
145 * P3. These groups can then be configured to transition between sleep, wait-on
146 * and active states by sending messages to the power bus. See Section 5.4.2
147 * Power Resources of TWL4030 TRM
148 */
149
150/* Processor groups */
151#define DEV_GRP_NULL 0x0
152#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
153#define DEV_GRP_P2 0x2 /* P2: all Modem devices */
154#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
155
156/* Resource groups */
157#define RES_GRP_RES 0x0 /* Reserved */
158#define RES_GRP_PP 0x1 /* Power providers */
159#define RES_GRP_RC 0x2 /* Reset and control */
160#define RES_GRP_PP_RC 0x3
161#define RES_GRP_PR 0x4 /* Power references */
162#define RES_GRP_PP_PR 0x5
163#define RES_GRP_RC_PR 0x6
164#define RES_GRP_ALL 0x7 /* All resource groups */
165
166#define RES_TYPE2_R0 0x0
167
168#define RES_TYPE_ALL 0x7
169
170/* Resource states */
171#define RES_STATE_WRST 0xF
172#define RES_STATE_ACTIVE 0xE
173#define RES_STATE_SLEEP 0x8
174#define RES_STATE_OFF 0x0
175
176/* Power resources */
177
178/* Power providers */
179#define RES_VAUX1 1
180#define RES_VAUX2 2
181#define RES_VAUX3 3
182#define RES_VAUX4 4
183#define RES_VMMC1 5
184#define RES_VMMC2 6
185#define RES_VPLL1 7
186#define RES_VPLL2 8
187#define RES_VSIM 9
188#define RES_VDAC 10
189#define RES_VINTANA1 11
190#define RES_VINTANA2 12
191#define RES_VINTDIG 13
192#define RES_VIO 14
193#define RES_VDD1 15
194#define RES_VDD2 16
195#define RES_VUSB_1V5 17
196#define RES_VUSB_1V8 18
197#define RES_VUSB_3V1 19
198#define RES_VUSBCP 20
199#define RES_REGEN 21
200/* Reset and control */
201#define RES_NRES_PWRON 22
202#define RES_CLKEN 23
203#define RES_SYSEN 24
204#define RES_HFCLKOUT 25
205#define RES_32KCLKOUT 26
206#define RES_RESET 27
207/* Power Reference */
208#define RES_Main_Ref 28
209
210#define TOTAL_RESOURCES 28
211/*
212 * Power Bus Message Format ... these can be sent individually by Linux,
213 * but are usually part of downloaded scripts that are run when various
214 * power events are triggered.
215 *
216 * Broadcast Message (16 Bits):
217 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
218 * RES_STATE[3:0]
219 *
220 * Singular Message (16 Bits):
221 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
222 */
223
224#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
225 ((devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
226 | (type) << 4 | (state))
227
228#define MSG_SINGULAR(devgrp, id, state) \
229 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
230
231#define MSG_BROADCAST_ALL(devgrp, state) \
232 ((devgrp) << 5 | (state))
233
234#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
235#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
236#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
237
Tom Rix8966eb42009-06-28 12:52:28 -0500238/* Power Managment Receiver */
Tom Rix2c155132009-06-28 12:52:30 -0500239#define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B
240#define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C
241#define TWL4030_PM_RECEIVER_SC_DETECT2 0x5D
242#define TWL4030_PM_RECEIVER_WATCHDOG_CFG 0x5E
243#define TWL4030_PM_RECEIVER_IT_CHECK_CFG 0x5F
244#define TWL4030_PM_RECEIVER_VIBRATOR_CFG 0x5F
245#define TWL4030_PM_RECEIVER_DC_TO_DC_CFG 0x61
246#define TWL4030_PM_RECEIVER_VDD1_TRIM1 0x62
247#define TWL4030_PM_RECEIVER_VDD1_TRIM2 0x63
248#define TWL4030_PM_RECEIVER_VDD2_TRIM1 0x64
249#define TWL4030_PM_RECEIVER_VDD2_TRIM2 0x65
250#define TWL4030_PM_RECEIVER_VIO_TRIM1 0x66
251#define TWL4030_PM_RECEIVER_VIO_TRIM2 0x67
252#define TWL4030_PM_RECEIVER_MISC_CFG 0x68
253#define TWL4030_PM_RECEIVER_LS_TST_A 0x69
254#define TWL4030_PM_RECEIVER_LS_TST_B 0x6A
255#define TWL4030_PM_RECEIVER_LS_TST_C 0x6B
256#define TWL4030_PM_RECEIVER_LS_TST_D 0x6C
257#define TWL4030_PM_RECEIVER_BB_CFG 0x6D
258#define TWL4030_PM_RECEIVER_MISC_TST 0x6E
259#define TWL4030_PM_RECEIVER_TRIM1 0x6F
260#define TWL4030_PM_RECEIVER_TRIM2 0x70
261#define TWL4030_PM_RECEIVER_DC_DC_TIMEOUT 0x71
262#define TWL4030_PM_RECEIVER_VAUX1_DEV_GRP 0x72
263#define TWL4030_PM_RECEIVER_VAUX1_TYPE 0x73
264#define TWL4030_PM_RECEIVER_VAUX1_REMAP 0x74
265#define TWL4030_PM_RECEIVER_VAUX1_DEDICATED 0x75
266#define TWL4030_PM_RECEIVER_VAUX2_DEV_GRP 0x76
267#define TWL4030_PM_RECEIVER_VAUX2_TYPE 0x77
268#define TWL4030_PM_RECEIVER_VAUX2_REMAP 0x78
269#define TWL4030_PM_RECEIVER_VAUX2_DEDICATED 0x79
270#define TWL4030_PM_RECEIVER_VAUX3_DEV_GRP 0x7A
271#define TWL4030_PM_RECEIVER_VAUX3_TYPE 0x7B
272#define TWL4030_PM_RECEIVER_VAUX3_REMAP 0x7C
273#define TWL4030_PM_RECEIVER_VAUX3_DEDICATED 0x7D
274#define TWL4030_PM_RECEIVER_VAUX4_DEV_GRP 0x7E
275#define TWL4030_PM_RECEIVER_VAUX4_TYPE 0x7F
276#define TWL4030_PM_RECEIVER_VAUX4_REMAP 0x80
277#define TWL4030_PM_RECEIVER_VAUX4_DEDICATED 0x81
278#define TWL4030_PM_RECEIVER_VMMC1_DEV_GRP 0x82
279#define TWL4030_PM_RECEIVER_VMMC1_TYPE 0x83
280#define TWL4030_PM_RECEIVER_VMMC1_REMAP 0x84
281#define TWL4030_PM_RECEIVER_VMMC1_DEDICATED 0x85
282#define TWL4030_PM_RECEIVER_VMMC2_DEV_GRP 0x86
283#define TWL4030_PM_RECEIVER_VMMC2_TYPE 0x87
284#define TWL4030_PM_RECEIVER_VMMC2_REMAP 0x88
285#define TWL4030_PM_RECEIVER_VMMC2_DEDICATED 0x89
286#define TWL4030_PM_RECEIVER_VPLL1_DEV_GRP 0x8A
287#define TWL4030_PM_RECEIVER_VPLL1_TYPE 0x8B
288#define TWL4030_PM_RECEIVER_VPLL1_REMAP 0x8C
289#define TWL4030_PM_RECEIVER_VPLL1_DEDICATED 0x8D
290#define TWL4030_PM_RECEIVER_VPLL2_DEV_GRP 0x8E
291#define TWL4030_PM_RECEIVER_VPLL2_TYPE 0x8F
292#define TWL4030_PM_RECEIVER_VPLL2_REMAP 0x90
293#define TWL4030_PM_RECEIVER_VPLL2_DEDICATED 0x91
294#define TWL4030_PM_RECEIVER_VSIM_DEV_GRP 0x92
295#define TWL4030_PM_RECEIVER_VSIM_TYPE 0x93
296#define TWL4030_PM_RECEIVER_VSIM_REMAP 0x94
297#define TWL4030_PM_RECEIVER_VSIM_DEDICATED 0x95
298#define TWL4030_PM_RECEIVER_VDAC_DEV_GRP 0x96
299#define TWL4030_PM_RECEIVER_VDAC_TYPE 0x97
300#define TWL4030_PM_RECEIVER_VDAC_REMAP 0x98
301#define TWL4030_PM_RECEIVER_VDAC_DEDICATED 0x99
302#define TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP 0x9A
303#define TWL4030_PM_RECEIVER_VINTANA1_TYP 0x9B
304#define TWL4030_PM_RECEIVER_VINTANA1_REMAP 0x9C
305#define TWL4030_PM_RECEIVER_VINTANA1_DEDICATED 0x9D
306#define TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP 0x9E
307#define TWL4030_PM_RECEIVER_VINTANA2_TYPE 0x9F
308#define TWL4030_PM_RECEIVER_VINTANA2_REMAP 0xA0
309#define TWL4030_PM_RECEIVER_VINTANA2_DEDICATED 0xA1
310#define TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP 0xA2
311#define TWL4030_PM_RECEIVER_VINTDIG_TYPE 0xA3
312#define TWL4030_PM_RECEIVER_VINTDIG_REMAP 0xA4
313#define TWL4030_PM_RECEIVER_VINTDIG_DEDICATED 0xA5
314#define TWL4030_PM_RECEIVER_VIO_DEV_GRP 0xA6
315#define TWL4030_PM_RECEIVER_VIO_TYPE 0xA7
316#define TWL4030_PM_RECEIVER_VIO_REMAP 0xA8
317#define TWL4030_PM_RECEIVER_VIO_CFG 0xA9
318#define TWL4030_PM_RECEIVER_VIO_MISC_CFG 0xAA
319#define TWL4030_PM_RECEIVER_VIO_TEST1 0xAB
320#define TWL4030_PM_RECEIVER_VIO_TEST2 0xAC
321#define TWL4030_PM_RECEIVER_VIO_OSC 0xAD
322#define TWL4030_PM_RECEIVER_VIO_RESERVED 0xAE
323#define TWL4030_PM_RECEIVER_VIO_VSEL 0xAF
324#define TWL4030_PM_RECEIVER_VDD1_DEV_GRP 0xB0
325#define TWL4030_PM_RECEIVER_VDD1_TYPE 0xB1
326#define TWL4030_PM_RECEIVER_VDD1_REMAP 0xB2
327#define TWL4030_PM_RECEIVER_VDD1_CFG 0xB3
328#define TWL4030_PM_RECEIVER_VDD1_MISC_CFG 0xB4
329#define TWL4030_PM_RECEIVER_VDD1_TEST1 0xB5
330#define TWL4030_PM_RECEIVER_VDD1_TEST2 0xB6
331#define TWL4030_PM_RECEIVER_VDD1_OSC 0xB7
332#define TWL4030_PM_RECEIVER_VDD1_RESERVED 0xB8
333#define TWL4030_PM_RECEIVER_VDD1_VSEL 0xB9
334#define TWL4030_PM_RECEIVER_VDD1_VMODE_CFG 0xBA
335#define TWL4030_PM_RECEIVER_VDD1_VFLOOR 0xBB
336#define TWL4030_PM_RECEIVER_VDD1_VROOF 0xBC
337#define TWL4030_PM_RECEIVER_VDD1_STEP 0xBD
338#define TWL4030_PM_RECEIVER_VDD2_DEV_GRP 0xBE
339#define TWL4030_PM_RECEIVER_VDD2_TYPE 0xBF
340#define TWL4030_PM_RECEIVER_VDD2_REMAP 0xC0
341#define TWL4030_PM_RECEIVER_VDD2_CFG 0xC1
342#define TWL4030_PM_RECEIVER_VDD2_MISC_CFG 0xC2
343#define TWL4030_PM_RECEIVER_VDD2_TEST1 0xC3
344#define TWL4030_PM_RECEIVER_VDD2_TEST2 0xC4
345#define TWL4030_PM_RECEIVER_VDD2_OSC 0xC5
346#define TWL4030_PM_RECEIVER_VDD2_RESERVED 0xC6
347#define TWL4030_PM_RECEIVER_VDD2_VSEL 0xC7
348#define TWL4030_PM_RECEIVER_VDD2_VMODE_CFG 0xC8
349#define TWL4030_PM_RECEIVER_VDD2_VFLOOR 0xC9
350#define TWL4030_PM_RECEIVER_VDD2_VROOF 0xCA
351#define TWL4030_PM_RECEIVER_VDD2_STEP 0xCB
Tom Rix8966eb42009-06-28 12:52:28 -0500352#define TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP 0xCC
353#define TWL4030_PM_RECEIVER_VUSB1V5_TYPE 0xCD
354#define TWL4030_PM_RECEIVER_VUSB1V5_REMAP 0xCE
355#define TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP 0xCF
356#define TWL4030_PM_RECEIVER_VUSB1V8_TYPE 0xD0
357#define TWL4030_PM_RECEIVER_VUSB1V8_REMAP 0xD1
358#define TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP 0xD2
359#define TWL4030_PM_RECEIVER_VUSB3V1_TYPE 0xD3
360#define TWL4030_PM_RECEIVER_VUSB3V1_REMAP 0xD4
361#define TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP 0xD5
Tom Rix2c155132009-06-28 12:52:30 -0500362#define TWL4030_PM_RECEIVER_VUSBCP_TYPE 0xD6
363#define TWL4030_PM_RECEIVER_VUSBCP_REMAP 0xD7
Tom Rix8966eb42009-06-28 12:52:28 -0500364#define TWL4030_PM_RECEIVER_VUSB_DEDICATED1 0xD8
365#define TWL4030_PM_RECEIVER_VUSB_DEDICATED2 0xD9
Tom Rix2c155132009-06-28 12:52:30 -0500366#define TWL4030_PM_RECEIVER_REGEN_DEV_GRP 0xDA
367#define TWL4030_PM_RECEIVER_REGEN_TYPE 0xDB
368#define TWL4030_PM_RECEIVER_REGEN_REMAP 0xDC
369#define TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP 0xDD
370#define TWL4030_PM_RECEIVER_NRESPWRON_TYPE 0xDE
371#define TWL4030_PM_RECEIVER_NRESPWRON_REMAP 0xDF
372#define TWL4030_PM_RECEIVER_CLKEN_DEV_GRP 0xE0
373#define TWL4030_PM_RECEIVER_CLKEN_TYPE 0xE1
374#define TWL4030_PM_RECEIVER_CLKEN_REMAP 0xE2
375#define TWL4030_PM_RECEIVER_SYSEN_DEV_GRP 0xE3
376#define TWL4030_PM_RECEIVER_SYSEN_TYPE 0xE4
377#define TWL4030_PM_RECEIVER_SYSEN_REMAP 0xE5
378#define TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP 0xE6
379#define TWL4030_PM_RECEIVER_HFCLKOUT_TYPE 0xE7
380#define TWL4030_PM_RECEIVER_HFCLKOUT_REMAP 0xE8
381#define TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP 0xE9
382#define TWL4030_PM_RECEIVER_32KCLKOUT_TYPE 0xEA
383#define TWL4030_PM_RECEIVER_32KCLKOUT_REMAP 0xEB
384#define TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GRP 0xEC
385#define TWL4030_PM_RECEIVER_TRITON_RESET_TYPE 0xED
386#define TWL4030_PM_RECEIVER_TRITON_RESET_REMAP 0xEE
387#define TWL4030_PM_RECEIVER_MAINREF_DEV_GRP 0xEF
388#define TWL4030_PM_RECEIVER_MAINREF_TYPE 0xF0
389#define TWL4030_PM_RECEIVER_MAINREF_REMAP 0xF1
390
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700391/* Voltage Selection in PM Receiver Module */
392#define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05
Paul Kocialkowski71bfb0f2014-10-28 16:10:59 +0100393#define TWL4030_PM_RECEIVER_VAUX2_VSEL_28 0x09
394#define TWL4030_PM_RECEIVER_VAUX3_VSEL_18 0x01
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700395#define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03
396#define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05
397#define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03
398#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02
Ash Charles528cdca2011-09-28 06:47:16 +0000399#define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03
Paul Kocialkowski2ed8c872014-10-28 18:14:23 +0100400#define TWL4030_PM_RECEIVER_VMMC2_VSEL_30 0x0B
401#define TWL4030_PM_RECEIVER_VMMC2_VSEL_32 0x0C
Pali Rohár318e70e2012-10-19 02:00:06 +0000402#define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700403
404/* Device Selection in PM Receiver Module */
405#define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20
406#define TWL4030_PM_RECEIVER_DEV_GRP_ALL 0xE0
407
Tom Rix2c155132009-06-28 12:52:30 -0500408/* LED */
409#define TWL4030_LED_LEDEN 0xEE
Grazvydas Ignotasead39d72009-12-10 17:10:21 +0200410#define TWL4030_LED_LEDEN_LEDAON (1 << 0)
411#define TWL4030_LED_LEDEN_LEDBON (1 << 1)
412#define TWL4030_LED_LEDEN_LEDAPWM (1 << 4)
413#define TWL4030_LED_LEDEN_LEDBPWM (1 << 5)
Tom Rix8966eb42009-06-28 12:52:28 -0500414
415/* Keypad */
416#define TWL4030_KEYPAD_KEYP_CTRL_REG 0xD2
417#define TWL4030_KEYPAD_KEY_DEB_REG 0xD3
418#define TWL4030_KEYPAD_LONG_KEY_REG1 0xD4
419#define TWL4030_KEYPAD_LK_PTV_REG 0xD5
420#define TWL4030_KEYPAD_TIME_OUT_REG1 0xD6
421#define TWL4030_KEYPAD_TIME_OUT_REG2 0xD7
422#define TWL4030_KEYPAD_KBC_REG 0xD8
423#define TWL4030_KEYPAD_KBR_REG 0xD9
424#define TWL4030_KEYPAD_KEYP_SMS 0xDA
425#define TWL4030_KEYPAD_FULL_CODE_7_0 0xDB
426#define TWL4030_KEYPAD_FULL_CODE_15_8 0xDC
427#define TWL4030_KEYPAD_FULL_CODE_23_16 0xDD
428#define TWL4030_KEYPAD_FULL_CODE_31_24 0xDE
429#define TWL4030_KEYPAD_FULL_CODE_39_32 0xDF
430#define TWL4030_KEYPAD_FULL_CODE_47_40 0xE0
431#define TWL4030_KEYPAD_FULL_CODE_55_48 0xE1
432#define TWL4030_KEYPAD_FULL_CODE_63_56 0xE2
433#define TWL4030_KEYPAD_KEYP_ISR1 0xE3
434#define TWL4030_KEYPAD_KEYP_IMR1 0xE4
435#define TWL4030_KEYPAD_KEYP_ISR2 0xE5
436#define TWL4030_KEYPAD_KEYP_IMR2 0xE6
437#define TWL4030_KEYPAD_KEYP_SIR 0xE7
438#define TWL4030_KEYPAD_KEYP_EDR 0xE8
439#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0xE9
440
441#define TWL4030_KEYPAD_CTRL_KBD_ON (1 << 6)
442#define TWL4030_KEYPAD_CTRL_RP_EN (1 << 5)
443#define TWL4030_KEYPAD_CTRL_TOLE_EN (1 << 4)
444#define TWL4030_KEYPAD_CTRL_TOE_EN (1 << 3)
445#define TWL4030_KEYPAD_CTRL_LK_EN (1 << 2)
446#define TWL4030_KEYPAD_CTRL_SOFTMODEN (1 << 1)
447#define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0)
448
449/* USB */
Tom Rixbffbb2a2009-10-31 12:37:40 -0500450#define TWL4030_USB_VENDOR_ID_LO 0x00
451#define TWL4030_USB_VENDOR_ID_HI 0x01
452#define TWL4030_USB_PRODUCT_ID_LO 0x02
453#define TWL4030_USB_PRODUCT_ID_HI 0x03
454#define TWL4030_USB_FUNC_CTRL 0x04
455#define TWL4030_USB_FUNC_CTRL_SET 0x05
456#define TWL4030_USB_FUNC_CTRL_CLR 0x06
457#define TWL4030_USB_IFC_CTRL 0x07
458#define TWL4030_USB_IFC_CTRL_SET 0x08
459#define TWL4030_USB_IFC_CTRL_CLR 0x09
460#define TWL4030_USB_OTG_CTRL 0x0A
461#define TWL4030_USB_OTG_CTRL_SET 0x0B
462#define TWL4030_USB_OTG_CTRL_CLR 0x0C
463#define TWL4030_USB_USB_INT_EN_RISE 0x0D
464#define TWL4030_USB_USB_INT_EN_RISE_SET 0x0E
465#define TWL4030_USB_USB_INT_EN_RISE_CLR 0x0F
466#define TWL4030_USB_USB_INT_EN_FALL 0x10
467#define TWL4030_USB_USB_INT_EN_FALL_SET 0x11
468#define TWL4030_USB_USB_INT_EN_FALL_CLR 0x12
469#define TWL4030_USB_USB_INT_STS 0x13
470#define TWL4030_USB_USB_INT_LATCH 0x14
471#define TWL4030_USB_DEBUG 0x15
472#define TWL4030_USB_SCRATCH_REG 0x16
473#define TWL4030_USB_SCRATCH_REG_SET 0x17
474#define TWL4030_USB_SCRATCH_REG_CLR 0x18
475#define TWL4030_USB_CARKIT_CTRL 0x19
476#define TWL4030_USB_CARKIT_CTRL_SET 0x1A
477#define TWL4030_USB_CARKIT_CTRL_CLR 0x1B
478#define TWL4030_USB_CARKIT_INT_DELAY 0x1C
479#define TWL4030_USB_CARKIT_INT_EN 0x1D
480#define TWL4030_USB_CARKIT_INT_EN_SET 0x1E
481#define TWL4030_USB_CARKIT_INT_EN_CLR 0x1F
482#define TWL4030_USB_CARKIT_INT_STS 0x20
483#define TWL4030_USB_CARKIT_INT_LATCH 0x21
484#define TWL4030_USB_CARKIT_PLS_CTRL 0x22
485#define TWL4030_USB_CARKIT_PLS_CTRL_SET 0x23
486#define TWL4030_USB_CARKIT_PLS_CTRL_CLR 0x24
487#define TWL4030_USB_TRANS_POS_WIDTH 0x25
488#define TWL4030_USB_TRANS_NEG_WIDTH 0x26
489#define TWL4030_USB_RCV_PLTY_RECOVERY 0x27
490#define TWL4030_USB_MCPC_CTRL 0x30
491#define TWL4030_USB_MCPC_CTRL_SET 0x31
492#define TWL4030_USB_MCPC_CTRL_CLR 0x32
493#define TWL4030_USB_MCPC_IO_CTRL 0x33
494#define TWL4030_USB_MCPC_IO_CTRL_SET 0x34
495#define TWL4030_USB_MCPC_IO_CTRL_CLR 0x35
496#define TWL4030_USB_MCPC_CTRL2 0x36
497#define TWL4030_USB_MCPC_CTRL2_SET 0x37
498#define TWL4030_USB_MCPC_CTRL2_CLR 0x38
499#define TWL4030_USB_OTHER_FUNC_CTRL 0x80
500#define TWL4030_USB_OTHER_FUNC_CTRL_SET 0x81
501#define TWL4030_USB_OTHER_FUNC_CTRL_CLR 0x82
502#define TWL4030_USB_OTHER_IFC_CTRL 0x83
503#define TWL4030_USB_OTHER_IFC_CTRL_SET 0x84
504#define TWL4030_USB_OTHER_IFC_CTRL_CLR 0x85
505#define TWL4030_USB_OTHER_INT_EN_RISE_SET 0x87
506#define TWL4030_USB_OTHER_INT_EN_RISE_CLR 0x88
507#define TWL4030_USB_OTHER_INT_EN_FALL 0x89
508#define TWL4030_USB_OTHER_INT_EN_FALL_SET 0x8A
509#define TWL4030_USB_OTHER_INT_EN_FALL_CLR 0x8B
510#define TWL4030_USB_OTHER_INT_STS 0x8C
511#define TWL4030_USB_OTHER_INT_LATCH 0x8D
512#define TWL4030_USB_ID_STATUS 0x96
513#define TWL4030_USB_CARKIT_SM_1_INT_EN 0x97
514#define TWL4030_USB_CARKIT_SM_1_INT_EN_SET 0x98
515#define TWL4030_USB_CARKIT_SM_1_INT_EN_CLR 0x99
516#define TWL4030_USB_CARKIT_SM_1_INT_STS 0x9A
517#define TWL4030_USB_CARKIT_SM_1_INT_LATCH 0x9B
518#define TWL4030_USB_CARKIT_SM_2_INT_EN 0x9C
519#define TWL4030_USB_CARKIT_SM_2_INT_EN_SET 0x9D
520#define TWL4030_USB_CARKIT_SM_2_INT_EN_CLR 0x9E
521#define TWL4030_USB_CARKIT_SM_2_INT_STS 0x9F
522#define TWL4030_USB_CARKIT_SM_2_INT_LATCH 0xA0
523#define TWL4030_USB_CARKIT_SM_CTRL 0xA1
524#define TWL4030_USB_CARKIT_SM_CTRL_SET 0xA2
525#define TWL4030_USB_CARKIT_SM_CTRL_CLR 0xA3
526#define TWL4030_USB_CARKIT_SM_CMD 0xA4
527#define TWL4030_USB_CARKIT_SM_CMD_SET 0xA5
528#define TWL4030_USB_CARKIT_SM_CMD_CLR 0xA6
529#define TWL4030_USB_CARKIT_SM_CMD_STS 0xA7
530#define TWL4030_USB_CARKIT_SM_STATUS 0xA8
531#define TWL4030_USB_CARKIT_SM_ERR_STATUS 0xAA
532#define TWL4030_USB_CARKIT_SM_CTRL_STATE 0xAB
533#define TWL4030_USB_POWER_CTRL 0xAC
534#define TWL4030_USB_POWER_CTRL_SET 0xAD
535#define TWL4030_USB_POWER_CTRL_CLR 0xAE
536#define TWL4030_USB_OTHER_IFC_CTRL2 0xAF
537#define TWL4030_USB_OTHER_IFC_CTRL2_SET 0xB0
538#define TWL4030_USB_OTHER_IFC_CTRL2_CLR 0xB1
539#define TWL4030_USB_REG_CTRL_EN 0xB2
540#define TWL4030_USB_REG_CTRL_EN_SET 0xB3
541#define TWL4030_USB_REG_CTRL_EN_CLR 0xB4
542#define TWL4030_USB_REG_CTRL_ERROR 0xB5
543#define TWL4030_USB_OTHER_FUNC_CTRL2 0xB8
544#define TWL4030_USB_OTHER_FUNC_CTRL2_SET 0xB9
545#define TWL4030_USB_OTHER_FUNC_CTRL2_CLR 0xBA
546#define TWL4030_USB_CARKIT_ANA_CTRL 0xBB
547#define TWL4030_USB_CARKIT_ANA_CTRL_SET 0xBC
548#define TWL4030_USB_CARKIT_ANA_CTRL_CLR 0xBD
549#define TWL4030_USB_VBUS_DEBOUNCE 0xC0
550#define TWL4030_USB_ID_DEBOUNCE 0xC1
551#define TWL4030_USB_TPH_DP_CON_MIN 0xC2
552#define TWL4030_USB_TPH_DP_CON_MAX 0xC3
553#define TWL4030_USB_TCR_DP_CON_MIN 0xC4
554#define TWL4030_USB_TCR_DP_CON_MAX 0xC5
555#define TWL4030_USB_TPH_DP_PD_SHORT 0xC6
556#define TWL4030_USB_TPH_CMD_DLY 0xC7
557#define TWL4030_USB_TPH_DET_RST 0xC8
558#define TWL4030_USB_TPH_AUD_BIAS 0xC9
559#define TWL4030_USB_TCR_UART_DET_MIN 0xCA
560#define TWL4030_USB_TCR_UART_DET_MAX 0xCB
561#define TWL4030_USB_TPH_ID_INT_PW 0xCD
562#define TWL4030_USB_TACC_ID_INT_WAIT 0xCE
563#define TWL4030_USB_TACC_ID_INT_PW 0xCF
564#define TWL4030_USB_TPH_CMD_WAIT 0xD0
565#define TWL4030_USB_TPH_ACK_WAIT 0xD1
566#define TWL4030_USB_TPH_DP_DISC_DET 0xD2
567#define TWL4030_USB_VBAT_TIMER 0xD3
568#define TWL4030_USB_CARKIT_4W_DEBUG 0xE0
569#define TWL4030_USB_CARKIT_5W_DEBUG 0xE1
570#define TWL4030_USB_PHY_PWR_CTRL 0xFD
571#define TWL4030_USB_PHY_CLK_CTRL 0xFE
572#define TWL4030_USB_PHY_CLK_CTRL_STS 0xFF
Tom Rix8966eb42009-06-28 12:52:28 -0500573
Nikita Kiryanov41b13bc2012-12-02 13:59:18 +0200574/* GPIO */
575#define TWL4030_GPIO_GPIODATAIN1 0x00
576#define TWL4030_GPIO_GPIODATAIN2 0x01
577#define TWL4030_GPIO_GPIODATAIN3 0x02
578#define TWL4030_GPIO_GPIODATADIR1 0x03
579#define TWL4030_GPIO_GPIODATADIR2 0x04
580#define TWL4030_GPIO_GPIODATADIR3 0x05
581#define TWL4030_GPIO_GPIODATAOUT1 0x06
582#define TWL4030_GPIO_GPIODATAOUT2 0x07
583#define TWL4030_GPIO_GPIODATAOUT3 0x08
584#define TWL4030_GPIO_CLEARGPIODATAOUT1 0x09
585#define TWL4030_GPIO_CLEARGPIODATAOUT2 0x0A
586#define TWL4030_GPIO_CLEARGPIODATAOUT3 0x0B
587#define TWL4030_GPIO_SETGPIODATAOUT1 0x0C
588#define TWL4030_GPIO_SETGPIODATAOUT2 0x0D
589#define TWL4030_GPIO_SETGPIODATAOUT3 0x0E
590#define TWL4030_GPIO_GPIO_DEBEN1 0x0F
591#define TWL4030_GPIO_GPIO_DEBEN2 0x10
592#define TWL4030_GPIO_GPIO_DEBEN3 0x11
593#define TWL4030_GPIO_GPIO_CTRL 0x12
594#define TWL4030_GPIO_GPIOPUPDCTR1 0x13
595#define TWL4030_GPIO_GPIOPUPDCTR2 0x14
596#define TWL4030_GPIO_GPIOPUPDCTR3 0x15
597#define TWL4030_GPIO_GPIOPUPDCTR4 0x16
598#define TWL4030_GPIO_GPIOPUPDCTR5 0x17
599#define TWL4030_GPIO_GPIO_ISR1A 0x19
600#define TWL4030_GPIO_GPIO_ISR2A 0x1A
601#define TWL4030_GPIO_GPIO_ISR3A 0x1B
602#define TWL4030_GPIO_GPIO_IMR1A 0x1C
603#define TWL4030_GPIO_GPIO_IMR2A 0x1D
604#define TWL4030_GPIO_GPIO_IMR3A 0x1E
605#define TWL4030_GPIO_GPIO_ISR1B 0x1F
606#define TWL4030_GPIO_GPIO_ISR2B 0x20
607#define TWL4030_GPIO_GPIO_ISR3B 0x21
608#define TWL4030_GPIO_GPIO_IMR1B 0x22
609#define TWL4030_GPIO_GPIO_IMR2B 0x23
610#define TWL4030_GPIO_GPIO_IMR3B 0x24
611#define TWL4030_GPIO_GPIO_EDR1 0x28
612#define TWL4030_GPIO_GPIO_EDR2 0x29
613#define TWL4030_GPIO_GPIO_EDR3 0x2A
614#define TWL4030_GPIO_GPIO_EDR4 0x2B
615#define TWL4030_GPIO_GPIO_EDR5 0x2C
616#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2D
617
Tom Rix8966eb42009-06-28 12:52:28 -0500618/*
619 * Convience functions to read and write from TWL4030
620 *
621 * chip_no is the i2c address, it must be one of the chip addresses
622 * defined at the top of this file with the prefix TWL4030_CHIP_
623 * examples are TWL4030_CHIP_PM_RECEIVER and TWL4030_CHIP_KEYPAD
624 *
625 * val is the data either written to or read from the twl4030
626 *
627 * reg is the register to act on, it must be one of the defines
628 * above and with the format TWL4030_<chip suffix>_<register name>
629 * examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
630 * TWL4030_LED_LEDEN.
631 */
Nishanth Menon0208aaf2013-03-26 05:20:49 +0000632static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
Tom Rix8966eb42009-06-28 12:52:28 -0500633{
634 return i2c_write(chip_no, reg, 1, &val, 1);
635}
636
Nishanth Menonb29c2f02013-03-26 05:20:50 +0000637static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
Tom Rix8966eb42009-06-28 12:52:28 -0500638{
639 return i2c_read(chip_no, reg, 1, val, 1);
640}
641
Tom Rix2c155132009-06-28 12:52:30 -0500642/*
643 * Power
644 */
645
Tom Rixcd782632009-06-28 12:52:29 -0500646/* For hardware resetting */
647void twl4030_power_reset_init(void);
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700648/* For setting device group and voltage */
649void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
650 u8 dev_grp, u8 dev_grp_sel);
Tom Rix2c155132009-06-28 12:52:30 -0500651/* For initializing power device */
652void twl4030_power_init(void);
Tom Rixfccc0fc2009-06-28 12:52:31 -0500653/* For initializing mmc power */
654void twl4030_power_mmc_init(void);
655
Tom Rix2c155132009-06-28 12:52:30 -0500656/*
657 * LED
658 */
Grazvydas Ignotasead39d72009-12-10 17:10:21 +0200659void twl4030_led_init(unsigned char ledon_mask);
Tom Rixcd782632009-06-28 12:52:29 -0500660
Tom Rixbffbb2a2009-10-31 12:37:40 -0500661/*
662 * USB
663 */
664int twl4030_usb_ulpi_init(void);
665
Tom Rix8966eb42009-06-28 12:52:28 -0500666#endif /* TWL4030_H */