blob: 241ba69fa05e72c3b16f051a36e89bada1de7bac [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +09002/*
3 * Configuation settings for the Hitachi Solution Engine 7722
4 *
5 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +09006 */
7
8#ifndef __MS7722SE_H
9#define __MS7722SE_H
10
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090011#define CONFIG_CPU_SH7722 1
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090012
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020013#define CONFIG_DISPLAY_BOARDINFO
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090014#undef CONFIG_SHOW_BOOT_PROGRESS
15
16/* SMC9111 */
Ben Warren7194ab82009-10-04 22:37:03 -070017#define CONFIG_SMC91111
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090018#define CONFIG_SMC91111_BASE (0xB8000000)
19
20/* MEMORY */
21#define MS7722SE_SDRAM_BASE (0x8C000000)
22#define MS7722SE_FLASH_BASE_1 (0xA0000000)
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090023#define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024)
24
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090027
28/* SCIF */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090029#define CONFIG_CONS_SCIF0 1
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090030
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031#define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE)
32#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090033
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#undef CONFIG_SYS_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090035
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090037
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_SDRAM_BASE (MS7722SE_SDRAM_BASE)
39#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090040
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090042
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image
Wolfgang Denk53677ef2008-05-20 16:00:29 +020044 in Flash (NOT run time address in SDRAM) ?!? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* */
46#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090048
49/* FLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#undef CONFIG_SYS_FLASH_QUIET_TEST
51#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090052
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090054
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_MAX_FLASH_SECT 150 /* Max number of sectors on each
Wolfgang Denk53677ef2008-05-20 16:00:29 +020056 Flash chip */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090057
58/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_MAX_FLASH_BANKS 2
60#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
61 CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090062 }
63
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */
65#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */
66#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */
67#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090068
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090070
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090071#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020072#define CONFIG_ENV_SECT_SIZE (8 * 1024)
73#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
75#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020076#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090078
79/* Board Clock */
80#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090081#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090082
83#endif /* __MS7722SE_H */