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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocher3b5df502015-06-29 09:10:48 +02002/*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * (C) Copyright 2010
8 * Achim Ehrlich <aehrlich@taskit.de>
9 * taskit GmbH <www.taskit.de>
10 *
11 * (C) Copyright 2012
12 * Markus Hubig <mhubig@imko.de>
13 * IMKO GmbH <www.imko.de>
14 *
15 * (C) Copyright 2014
16 * Heiko Schocher <hs@denx.de>
17 * DENX Software Engineering GmbH
18 *
19 * Configuation settings for the smartweb.
Heiko Schocher3b5df502015-06-29 09:10:48 +020020 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25/*
26 * SoC must be defined first, before hardware.h is included.
27 * In this case SoC is defined in boards.cfg.
28 */
29#include <asm/hardware.h>
Heiko Schochere8b81ee2015-09-08 11:52:52 +020030#include <linux/sizes.h>
Heiko Schocher3b5df502015-06-29 09:10:48 +020031
32/*
33 * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
34 * program. Since the linker has to swallow that define, we must use a pure
35 * hex number here!
36 */
Heiko Schocher3b5df502015-06-29 09:10:48 +020037
38/* ARM asynchronous clock */
39#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
40#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
41
42/* misc settings */
Heiko Schocher3b5df502015-06-29 09:10:48 +020043
Heiko Schocher3b5df502015-06-29 09:10:48 +020044/*
45 * SDRAM: 1 bank, 64 MB, base address 0x20000000
46 * Already initialized before u-boot gets started.
47 */
Heiko Schocher3b5df502015-06-29 09:10:48 +020048#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
Heiko Schochere8b81ee2015-09-08 11:52:52 +020049#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M)
Heiko Schocher3b5df502015-06-29 09:10:48 +020050
51/*
52 * Perform a SDRAM Memtest from the start of SDRAM
53 * till the beginning of the U-Boot position in RAM.
54 */
Heiko Schocher3b5df502015-06-29 09:10:48 +020055
Heiko Schocher3b5df502015-06-29 09:10:48 +020056/* NAND flash settings */
Heiko Schocher3b5df502015-06-29 09:10:48 +020057#define CONFIG_SYS_MAX_NAND_DEVICE 1
58#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
59#define CONFIG_SYS_NAND_DBW_8
60#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
61#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
62#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
63#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
64
Heiko Schocher3b5df502015-06-29 09:10:48 +020065/* serial console */
Heiko Schocher3b5df502015-06-29 09:10:48 +020066#define CONFIG_USART_BASE ATMEL_BASE_DBGU
67#define CONFIG_USART_ID ATMEL_ID_SYS
Heiko Schocher3b5df502015-06-29 09:10:48 +020068
Heiko Schocher3b5df502015-06-29 09:10:48 +020069/* USB configuration */
70#define CONFIG_USB_ATMEL
71#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
72#define CONFIG_USB_OHCI_NEW
Heiko Schocher3b5df502015-06-29 09:10:48 +020073#define CONFIG_SYS_USB_OHCI_CPU_INIT
74#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
75#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
76#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Heiko Schochere8b81ee2015-09-08 11:52:52 +020077
Heiko Schochere8b81ee2015-09-08 11:52:52 +020078/* USB DFU support */
Heiko Schochere8b81ee2015-09-08 11:52:52 +020079
Heiko Schochere8b81ee2015-09-08 11:52:52 +020080#define CONFIG_USB_GADGET_AT91
81
82/* DFU class support */
Heiko Schochere8b81ee2015-09-08 11:52:52 +020083#define DFU_MANIFEST_POLL_TIMEOUT 25000
Heiko Schocher3b5df502015-06-29 09:10:48 +020084
85/* General Boot Parameter */
Heiko Schocher3b5df502015-06-29 09:10:48 +020086
87/*
Heiko Schocher3b5df502015-06-29 09:10:48 +020088 * Predefined environment variables.
89 * Usefull to define some easy to use boot commands.
90 */
91#define CONFIG_EXTRA_ENV_SETTINGS \
92 \
93 "basicargs=console=ttyS0,115200\0" \
94 \
Tom Rini43ede0b2017-10-22 17:55:07 -040095 "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"
Heiko Schocher3b5df502015-06-29 09:10:48 +020096
Heiko Schocher3b5df502015-06-29 09:10:48 +020097/*
98 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
99 * leaving the correct space for initial global data structure above that
100 * address while providing maximum stack area below.
101 */
Tom Rinieaf6ea62022-05-25 12:16:03 -0400102#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
103#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
Heiko Schocher3b5df502015-06-29 09:10:48 +0200104
Heiko Schocher3b5df502015-06-29 09:10:48 +0200105/* Defines for SPL */
Heiko Schocher3b5df502015-06-29 09:10:48 +0200106
Heiko Schocher3b5df502015-06-29 09:10:48 +0200107#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
Heiko Schochere8b81ee2015-09-08 11:52:52 +0200108#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
Heiko Schocher3b5df502015-06-29 09:10:48 +0200109#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
110#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
Heiko Schocher3b5df502015-06-29 09:10:48 +0200111
Heiko Schochere8b81ee2015-09-08 11:52:52 +0200112#define CONFIG_SYS_NAND_SIZE (SZ_256M)
Heiko Schocher3b5df502015-06-29 09:10:48 +0200113#define CONFIG_SYS_NAND_ECCSIZE 256
114#define CONFIG_SYS_NAND_ECCBYTES 3
Heiko Schocher3b5df502015-06-29 09:10:48 +0200115#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
116 48, 49, 50, 51, 52, 53, 54, 55, \
117 56, 57, 58, 59, 60, 61, 62, 63, }
118
Heiko Schocher3b5df502015-06-29 09:10:48 +0200119#define CONFIG_SYS_MASTER_CLOCK (198656000/2)
120#define AT91_PLL_LOCK_TIMEOUT 1000000
121#define CONFIG_SYS_AT91_PLLA 0x2060bf09
122#define CONFIG_SYS_MCKR 0x100
123#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
124#define CONFIG_SYS_AT91_PLLB 0x10483f0e
125
Heiko Schocher3b5df502015-06-29 09:10:48 +0200126#endif /* __CONFIG_H */