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Alex Margineana7fdac72021-01-27 13:00:00 +02001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP LS1028A-QDS device tree fragment for RCW x5xx
4 *
Vladimir Oltean66fd01f2021-09-17 14:27:13 +03005 * Copyright 2019-2021 NXP
Alex Margineana7fdac72021-01-27 13:00:00 +02006 */
7
8/*
9 * This setup is using SCH-28021 cards with VSC8514 QSGMII PHY in slot 2.
10 * This is only available on LS1028A QDS boards with lane B rework.
11 */
12&slot2 {
13 #include "fsl-sch-28021.dtsi"
14};
15
Michael Wallec816dd02021-10-13 18:14:15 +020016&enetc_port2 {
Vladimir Oltean39dca762021-06-29 20:53:11 +030017 status = "okay";
18};
19
Alex Margineana7fdac72021-01-27 13:00:00 +020020&mscc_felix {
21 status = "okay";
22};
23
24&mscc_felix_port0 {
25 status = "okay";
Vladimir Oltean681adaa2022-01-03 14:47:37 +020026 managed = "in-band-status";
Alex Margineana7fdac72021-01-27 13:00:00 +020027 phy-mode = "qsgmii";
Michael Wallefb19c6b2021-10-13 18:14:05 +020028 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
Alex Margineana7fdac72021-01-27 13:00:00 +020029};
30
31&mscc_felix_port1 {
32 status = "okay";
Vladimir Oltean681adaa2022-01-03 14:47:37 +020033 managed = "in-band-status";
Alex Margineana7fdac72021-01-27 13:00:00 +020034 phy-mode = "qsgmii";
Michael Wallefb19c6b2021-10-13 18:14:05 +020035 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
Alex Margineana7fdac72021-01-27 13:00:00 +020036};
37
38&mscc_felix_port2 {
39 status = "okay";
Vladimir Oltean681adaa2022-01-03 14:47:37 +020040 managed = "in-band-status";
Alex Margineana7fdac72021-01-27 13:00:00 +020041 phy-mode = "qsgmii";
Michael Wallefb19c6b2021-10-13 18:14:05 +020042 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
Alex Margineana7fdac72021-01-27 13:00:00 +020043};
44
45&mscc_felix_port3 {
46 status = "okay";
Vladimir Oltean681adaa2022-01-03 14:47:37 +020047 managed = "in-band-status";
Alex Margineana7fdac72021-01-27 13:00:00 +020048 phy-mode = "qsgmii";
Michael Wallefb19c6b2021-10-13 18:14:05 +020049 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
Alex Margineana7fdac72021-01-27 13:00:00 +020050};
Vladimir Oltean39dca762021-06-29 20:53:11 +030051
52&mscc_felix_port4 {
Michael Wallec816dd02021-10-13 18:14:15 +020053 ethernet = <&enetc_port2>;
Vladimir Oltean39dca762021-06-29 20:53:11 +030054 status = "okay";
55};