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goda.yusukee7101852008-03-05 17:08:20 +09001/*
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +02002Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
goda.yusukee7101852008-03-05 17:08:20 +09003
4Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
5eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
6are GPL, so this is, of course, GPL.
7
8
9==========================================================================
10
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +020011 dev/dp83902a.h
goda.yusukee7101852008-03-05 17:08:20 +090012
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +020013 National Semiconductor DP83902a ethernet chip
goda.yusukee7101852008-03-05 17:08:20 +090014
15==========================================================================
16####ECOSGPLCOPYRIGHTBEGIN####
17 -------------------------------------------
18 This file is part of eCos, the Embedded Configurable Operating System.
19 Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
20
21 eCos is free software; you can redistribute it and/or modify it under
22 the terms of the GNU General Public License as published by the Free
23 Software Foundation; either version 2 or (at your option) any later version.
24
25 eCos is distributed in the hope that it will be useful, but WITHOUT ANY
26 WARRANTY; without even the implied warranty of MERCHANTABILITY or
27 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
28 for more details.
29
30 You should have received a copy of the GNU General Public License along
31 with eCos; if not, write to the Free Software Foundation, Inc.,
32 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
33
34 As a special exception, if other files instantiate templates or use macros
35 or inline functions from this file, or you compile this file and link it
36 with other works to produce a work based on this file, this file does not
37 by itself cause the resulting work to be covered by the GNU General Public
38 License. However the source code for this file must still be made available
39 in accordance with section (3) of the GNU General Public License.
40
41 This exception does not invalidate any other reasons why a work based on
42 this file might be covered by the GNU General Public License.
43
44 Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
45 at http://sources.redhat.com/ecos/ecos-license/
46 -------------------------------------------
47####ECOSGPLCOPYRIGHTEND####
48####BSDCOPYRIGHTBEGIN####
49
50 -------------------------------------------
51
52 Portions of this software may have been derived from OpenBSD or other sources,
53 and are covered by the appropriate copyright disclaimers included herein.
54
55 -------------------------------------------
56
57####BSDCOPYRIGHTEND####
58==========================================================================
59#####DESCRIPTIONBEGIN####
60
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +020061 Author(s): gthomas
62 Contributors: gthomas, jskov
63 Date: 2001-06-13
goda.yusukee7101852008-03-05 17:08:20 +090064 Purpose:
65 Description:
66
67####DESCRIPTIONEND####
68
69==========================================================================
70
71*/
72
73/*
74 ------------------------------------------------------------------------
75 Macros for accessing DP registers
76 These can be overridden by the platform header
77*/
78
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +020079#ifndef __NE2000_BASE_H__
80#define __NE2000_BASE_H__
81
goda.yusukee7101852008-03-05 17:08:20 +090082#define bool int
goda.yusukee7101852008-03-05 17:08:20 +090083#define false 0
84#define true 1
85
Nobuhiro Iwamatsu702c85b2008-09-30 15:02:53 +090086/*
87 * Debugging details
88 *
89 * Set to perms of:
90 * 0 disables all debug output
91 * 1 for process debug output
92 * 2 for added data IO output: get_reg, put_reg
93 * 4 for packet allocation/free output
94 * 8 for only startup status, so we can tell we're installed OK
95 */
96#if 0
97#define DEBUG 0xf
98#else
99#define DEBUG 0
100#endif
101
102#if DEBUG & 1
103#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
104#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
105#define PRINTK(args...) printf(args)
106#else
107#define DEBUG_FUNCTION() do {} while(0)
108#define DEBUG_LINE() do {} while(0)
109#define PRINTK(args...)
110#endif
111
goda.yusukee7101852008-03-05 17:08:20 +0900112/* timeout for tx/rx in s */
113#define TOUT 5
114/* Ether MAC address size */
115#define ETHER_ADDR_LEN 6
116
117
118#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
119#define CYGACC_CALL_IF_DELAY_US(X) udelay(X)
120
121/* H/W infomation struct */
122typedef struct hw_info_t {
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200123 u32 offset;
124 u8 a0, a1, a2;
125 u32 flags;
goda.yusukee7101852008-03-05 17:08:20 +0900126} hw_info_t;
127
128typedef struct dp83902a_priv_data {
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200129 u8* base;
130 u8* data;
131 u8* reset;
132 int tx_next; /* First free Tx page */
133 int tx_int; /* Expecting interrupt from this buffer */
134 int rx_next; /* First free Rx page */
135 int tx1, tx2; /* Page numbers for Tx buffers */
136 u32 tx1_key, tx2_key; /* Used to ack when packet sent */
137 int tx1_len, tx2_len;
138 bool tx_started, running, hardwired_esa;
139 u8 esa[6];
140 void* plf_priv;
goda.yusukee7101852008-03-05 17:08:20 +0900141
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200142 /* Buffer allocation */
143 int tx_buf1, tx_buf2;
144 int rx_buf_start, rx_buf_end;
goda.yusukee7101852008-03-05 17:08:20 +0900145} dp83902a_priv_data_t;
146
goda.yusukee7101852008-03-05 17:08:20 +0900147/* ------------------------------------------------------------------------ */
148/* Register offsets */
149
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200150#define DP_CR 0x00
151#define DP_CLDA0 0x01
152#define DP_PSTART 0x01 /* write */
153#define DP_CLDA1 0x02
154#define DP_PSTOP 0x02 /* write */
155#define DP_BNDRY 0x03
156#define DP_TSR 0x04
157#define DP_TPSR 0x04 /* write */
158#define DP_NCR 0x05
159#define DP_TBCL 0x05 /* write */
160#define DP_FIFO 0x06
161#define DP_TBCH 0x06 /* write */
162#define DP_ISR 0x07
163#define DP_CRDA0 0x08
164#define DP_RSAL 0x08 /* write */
165#define DP_CRDA1 0x09
166#define DP_RSAH 0x09 /* write */
167#define DP_RBCL 0x0a /* write */
168#define DP_RBCH 0x0b /* write */
169#define DP_RSR 0x0c
170#define DP_RCR 0x0c /* write */
171#define DP_FER 0x0d
172#define DP_TCR 0x0d /* write */
173#define DP_CER 0x0e
174#define DP_DCR 0x0e /* write */
175#define DP_MISSED 0x0f
176#define DP_IMR 0x0f /* write */
177#define DP_DATAPORT 0x10 /* "eprom" data port */
goda.yusukee7101852008-03-05 17:08:20 +0900178
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200179#define DP_P1_CR 0x00
180#define DP_P1_PAR0 0x01
181#define DP_P1_PAR1 0x02
182#define DP_P1_PAR2 0x03
183#define DP_P1_PAR3 0x04
184#define DP_P1_PAR4 0x05
185#define DP_P1_PAR5 0x06
186#define DP_P1_CURP 0x07
187#define DP_P1_MAR0 0x08
188#define DP_P1_MAR1 0x09
189#define DP_P1_MAR2 0x0a
190#define DP_P1_MAR3 0x0b
191#define DP_P1_MAR4 0x0c
192#define DP_P1_MAR5 0x0d
193#define DP_P1_MAR6 0x0e
194#define DP_P1_MAR7 0x0f
goda.yusukee7101852008-03-05 17:08:20 +0900195
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200196#define DP_P2_CR 0x00
197#define DP_P2_PSTART 0x01
198#define DP_P2_CLDA0 0x01 /* write */
199#define DP_P2_PSTOP 0x02
200#define DP_P2_CLDA1 0x02 /* write */
201#define DP_P2_RNPP 0x03
202#define DP_P2_TPSR 0x04
203#define DP_P2_LNPP 0x05
204#define DP_P2_ACH 0x06
205#define DP_P2_ACL 0x07
206#define DP_P2_RCR 0x0c
207#define DP_P2_TCR 0x0d
208#define DP_P2_DCR 0x0e
209#define DP_P2_IMR 0x0f
goda.yusukee7101852008-03-05 17:08:20 +0900210
211/* Command register - common to all pages */
212
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200213#define DP_CR_STOP 0x01 /* Stop: software reset */
214#define DP_CR_START 0x02 /* Start: initialize device */
215#define DP_CR_TXPKT 0x04 /* Transmit packet */
216#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */
217#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */
218#define DP_CR_SEND 0x18 /* Send packet */
219#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */
220#define DP_CR_PAGE0 0x00 /* Page select */
221#define DP_CR_PAGE1 0x40
222#define DP_CR_PAGE2 0x80
223#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */
goda.yusukee7101852008-03-05 17:08:20 +0900224
225/* Data configuration register */
226
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200227#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */
228#define DP_DCR_BOS 0x02 /* 1=Little Endian */
229#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */
230#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */
231#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */
232#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */
233#define DP_DCR_FIFO_2 0x20
234#define DP_DCR_FIFO_4 0x40
235#define DP_DCR_FIFO_6 0x60
goda.yusukee7101852008-03-05 17:08:20 +0900236
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200237#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4)
goda.yusukee7101852008-03-05 17:08:20 +0900238
239/* Interrupt status register */
240
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200241#define DP_ISR_RxP 0x01 /* Packet received */
242#define DP_ISR_TxP 0x02 /* Packet transmitted */
243#define DP_ISR_RxE 0x04 /* Receive error */
244#define DP_ISR_TxE 0x08 /* Transmit error */
245#define DP_ISR_OFLW 0x10 /* Receive overflow */
246#define DP_ISR_CNT 0x20 /* Tally counters need emptying */
247#define DP_ISR_RDC 0x40 /* Remote DMA complete */
248#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */
goda.yusukee7101852008-03-05 17:08:20 +0900249
250/* Interrupt mask register */
251
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200252#define DP_IMR_RxP 0x01 /* Packet received */
253#define DP_IMR_TxP 0x02 /* Packet transmitted */
254#define DP_IMR_RxE 0x04 /* Receive error */
255#define DP_IMR_TxE 0x08 /* Transmit error */
256#define DP_IMR_OFLW 0x10 /* Receive overflow */
257#define DP_IMR_CNT 0x20 /* Tall counters need emptying */
258#define DP_IMR_RDC 0x40 /* Remote DMA complete */
goda.yusukee7101852008-03-05 17:08:20 +0900259
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200260#define DP_IMR_All 0x3F /* Everything but remote DMA */
goda.yusukee7101852008-03-05 17:08:20 +0900261
262/* Receiver control register */
263
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200264#define DP_RCR_SEP 0x01 /* Save bad(error) packets */
265#define DP_RCR_AR 0x02 /* Accept runt packets */
266#define DP_RCR_AB 0x04 /* Accept broadcast packets */
267#define DP_RCR_AM 0x08 /* Accept multicast packets */
268#define DP_RCR_PROM 0x10 /* Promiscuous mode */
269#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */
goda.yusukee7101852008-03-05 17:08:20 +0900270
271/* Receiver status register */
272
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200273#define DP_RSR_RxP 0x01 /* Packet received */
274#define DP_RSR_CRC 0x02 /* CRC error */
275#define DP_RSR_FRAME 0x04 /* Framing error */
276#define DP_RSR_FO 0x08 /* FIFO overrun */
277#define DP_RSR_MISS 0x10 /* Missed packet */
278#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */
279#define DP_RSR_DIS 0x40 /* Receiver disabled */
280#define DP_RSR_DFR 0x80 /* Receiver processing deferred */
goda.yusukee7101852008-03-05 17:08:20 +0900281
282/* Transmitter control register */
283
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200284#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */
285#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */
286#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */
287#define DP_TCR_INLOOP 0x04 /* Full internal loopback */
288#define DP_TCR_OUTLOOP 0x08 /* External loopback */
289#define DP_TCR_ATD 0x10 /* Auto transmit disable */
290#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */
goda.yusukee7101852008-03-05 17:08:20 +0900291
292/* Transmit status register */
293
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200294#define DP_TSR_TxP 0x01 /* Packet transmitted */
295#define DP_TSR_COL 0x04 /* Collision (at least one) */
296#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */
297#define DP_TSR_CRS 0x10 /* Lost carrier */
298#define DP_TSR_FU 0x20 /* FIFO underrun */
299#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */
300#define DP_TSR_OWC 0x80 /* Collision outside normal window */
goda.yusukee7101852008-03-05 17:08:20 +0900301
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200302#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */
303#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */
Nobuhiro Iwamatsu702c85b2008-09-30 15:02:53 +0900304
305/* Functions */
306int get_prom(u8* mac_addr, u8* base_addr);
307
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200308#endif /* __NE2000_BASE_H__ */