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wdenk1c437712004-01-16 00:30:56 +00001/*
2 * (C) Copyright 2004
3 * Reinhard Meyer, EMK Elektronik GmbH
4 * r.meyer@emk-elektronik.de
5 * www.emk-elektronik.de
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*****************************************************************************
27 * Date & Time support for internal RTC of MPC52xx
28 *****************************************************************************/
29/*#define DEBUG*/
30
31#include <common.h>
32#include <command.h>
33#include <rtc.h>
34
Michal Simek871c18d2008-07-14 19:45:37 +020035#if defined(CONFIG_CMD_DATE)
wdenk1c437712004-01-16 00:30:56 +000036
37/*****************************************************************************
38 * this structure should be defined in mpc5200.h ...
39 *****************************************************************************/
40typedef struct rtc5200 {
41 volatile ulong tsr; /* MBAR+0x800: time set register */
42 volatile ulong dsr; /* MBAR+0x804: data set register */
43 volatile ulong nysr; /* MBAR+0x808: new year and stopwatch register */
44 volatile ulong aier; /* MBAR+0x80C: alarm and interrupt enable register */
45 volatile ulong ctr; /* MBAR+0x810: current time register */
46 volatile ulong cdr; /* MBAR+0x814: current data register */
Mike Williams16263082011-07-22 04:01:30 +000047 volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interrupt register */
wdenk1c437712004-01-16 00:30:56 +000048 volatile ulong piber; /* MBAR+0x81C: periodic interrupt and bus error register */
49 volatile ulong trdr; /* MBAR+0x820: test register/divides register */
50} RTC5200;
51
52#define RTC_SET 0x02000000
53#define RTC_PAUSE 0x01000000
54
55/*****************************************************************************
56 * get time
57 *****************************************************************************/
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030058int rtc_get (struct rtc_time *tmp)
wdenk1c437712004-01-16 00:30:56 +000059{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060 RTC5200 *rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800);
wdenk1c437712004-01-16 00:30:56 +000061 ulong time, date, time2;
62
63 /* read twice to avoid getting a funny time when the second is just changing */
64 do {
65 time = rtc->ctr;
66 date = rtc->cdr;
67 time2 = rtc->ctr;
68 } while (time != time2);
69
70 tmp->tm_year = date & 0xfff;
71 tmp->tm_mon = (date >> 24) & 0xf;
72 tmp->tm_mday = (date >> 16) & 0x1f;
73 tmp->tm_wday = (date >> 21) & 7;
74 /* sunday is 7 in 5200 but 0 in rtc_time */
75 if (tmp->tm_wday == 7)
76 tmp->tm_wday = 0;
77 tmp->tm_hour = (time >> 16) & 0x1f;
78 tmp->tm_min = (time >> 8) & 0x3f;
79 tmp->tm_sec = time & 0x3f;
80
81 debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
82 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
83 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030084
85 return 0;
wdenk1c437712004-01-16 00:30:56 +000086}
87
88/*****************************************************************************
89 * set time
90 *****************************************************************************/
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +020091int rtc_set (struct rtc_time *tmp)
wdenk1c437712004-01-16 00:30:56 +000092{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 RTC5200 *rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800);
wdenk1c437712004-01-16 00:30:56 +000094 ulong time, date, year;
95
96 debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
97 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
98 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
99
100 time = (tmp->tm_hour << 16) | (tmp->tm_min << 8) | tmp->tm_sec;
101 date = (tmp->tm_mon << 16) | tmp->tm_mday;
102 if (tmp->tm_wday == 0)
103 date |= (7 << 8);
104 else
105 date |= (tmp->tm_wday << 8);
106 year = tmp->tm_year;
107
108 /* mask unwanted bits that might show up when rtc_time is corrupt */
109 time &= 0x001f3f3f;
110 date &= 0x001f071f;
111 year &= 0x00000fff;
112
113 /* pause and set the RTC */
114 rtc->nysr = year;
115 rtc->dsr = date | RTC_PAUSE;
116 udelay (1000);
117 rtc->dsr = date | RTC_PAUSE | RTC_SET;
118 udelay (1000);
119 rtc->dsr = date | RTC_PAUSE;
120 udelay (1000);
121 rtc->dsr = date;
122 udelay (1000);
123
124 rtc->tsr = time | RTC_PAUSE;
125 udelay (1000);
126 rtc->tsr = time | RTC_PAUSE | RTC_SET;
127 udelay (1000);
128 rtc->tsr = time | RTC_PAUSE;
129 udelay (1000);
130 rtc->tsr = time;
131 udelay (1000);
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200132
133 return 0;
wdenk1c437712004-01-16 00:30:56 +0000134}
135
136/*****************************************************************************
137 * reset rtc circuit
138 *****************************************************************************/
139void rtc_reset (void)
140{
141 return; /* nothing to do */
142}
143
Jon Loeliger068b60a2007-07-10 10:27:39 -0500144#endif