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wdenk78f66222002-08-27 10:27:51 +00001/*
2 * (C) Copyright 2000
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
26#ifdef CFG_NS16550_SERIAL
27
28#include <ns16550.h>
29#ifdef CFG_NS87308
30#include <ns87308.h>
31#endif
32
wdenk756f5862005-04-03 15:51:42 +000033#if !defined(CONFIG_CONS_INDEX)
34#error "No console index specified."
35#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
36#error "Invalid console index value."
wdenk78f66222002-08-27 10:27:51 +000037#endif
38
wdenk756f5862005-04-03 15:51:42 +000039#if CONFIG_CONS_INDEX == 1 && !defined(CFG_NS16550_COM1)
40#error "Console port 1 defined but not configured."
41#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_NS16550_COM2)
42#error "Console port 2 defined but not configured."
43#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_NS16550_COM3)
44#error "Console port 3 defined but not configured."
45#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_NS16550_COM4)
46#error "Console port 4 defined but not configured."
47#endif
48
49/* Note: The port number specified in the functions is 1 based.
50 * the array is 0 based.
51 */
52static NS16550_t serial_ports[4] = {
53#ifdef CFG_NS16550_COM1
54 (NS16550_t)CFG_NS16550_COM1,
55#else
56 NULL,
57#endif
58#ifdef CFG_NS16550_COM2
59 (NS16550_t)CFG_NS16550_COM2,
60#else
61 NULL,
62#endif
63#ifdef CFG_NS16550_COM3
64 (NS16550_t)CFG_NS16550_COM3,
65#else
66 NULL,
67#endif
68#ifdef CFG_NS16550_COM4
69 (NS16550_t)CFG_NS16550_COM4
70#else
71 NULL
72#endif
73};
74
75#define PORT serial_ports[port-1]
76#define CONSOLE (serial_ports[CONFIG_CONS_INDEX-1])
77
78static int calc_divisor (NS16550_t port)
wdenk78f66222002-08-27 10:27:51 +000079{
80 DECLARE_GLOBAL_DATA_PTR;
wdenk2e5983d2003-07-15 20:04:06 +000081#ifdef CONFIG_OMAP1510
82 /* If can't cleanly clock 115200 set div to 1 */
83 if ((CFG_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
wdenk756f5862005-04-03 15:51:42 +000084 port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */
wdenk2e5983d2003-07-15 20:04:06 +000085 return (1); /* return 1 for base divisor */
86 }
wdenk756f5862005-04-03 15:51:42 +000087 port->osc_12m_sel = 0; /* clear if previsouly set */
wdenk2e5983d2003-07-15 20:04:06 +000088#endif
wdenk6f213472003-08-29 22:00:43 +000089#ifdef CONFIG_OMAP1610
90 /* If can't cleanly clock 115200 set div to 1 */
91 if ((CFG_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) {
92 return (26); /* return 26 for base divisor */
93 }
94#endif
wdenk8ed96042005-01-09 23:16:25 +000095
96#ifdef CONFIG_APTIX
97#define MODE_X_DIV 13
98#else
99#define MODE_X_DIV 16
100#endif
101 return (CFG_NS16550_CLK / MODE_X_DIV / gd->baudrate);
102
wdenk2e5983d2003-07-15 20:04:06 +0000103}
wdenk78f66222002-08-27 10:27:51 +0000104
wdenk2e5983d2003-07-15 20:04:06 +0000105int serial_init (void)
106{
wdenk756f5862005-04-03 15:51:42 +0000107 int clock_divisor;
wdenk78f66222002-08-27 10:27:51 +0000108
109#ifdef CFG_NS87308
110 initialise_ns87308();
111#endif
112
wdenk756f5862005-04-03 15:51:42 +0000113#ifdef CFG_NS16550_COM1
114 clock_divisor = calc_divisor(serial_ports[0]);
115 NS16550_init(serial_ports[0], clock_divisor);
116#endif
117#ifdef CFG_NS16550_COM2
118 clock_divisor = calc_divisor(serial_ports[1]);
119 NS16550_init(serial_ports[1], clock_divisor);
120#endif
121#ifdef CFG_NS16550_COM3
122 clock_divisor = calc_divisor(serial_ports[2]);
123 NS16550_init(serial_ports[2], clock_divisor);
124#endif
125#ifdef CFG_NS16550_COM4
126 clock_divisor = calc_divisor(serial_ports[3]);
127 NS16550_init(serial_ports[3], clock_divisor);
128#endif
wdenk78f66222002-08-27 10:27:51 +0000129
130 return (0);
131}
132
133void
wdenk756f5862005-04-03 15:51:42 +0000134_serial_putc(const char c,const int port)
wdenk78f66222002-08-27 10:27:51 +0000135{
136 if (c == '\n')
wdenk756f5862005-04-03 15:51:42 +0000137 NS16550_putc(PORT, '\r');
wdenk78f66222002-08-27 10:27:51 +0000138
wdenk756f5862005-04-03 15:51:42 +0000139 NS16550_putc(PORT, c);
wdenk78f66222002-08-27 10:27:51 +0000140}
141
142void
wdenk756f5862005-04-03 15:51:42 +0000143_serial_putc_raw(const char c,const int port)
144{
145 NS16550_putc(PORT, c);
146}
147
148void
149_serial_puts (const char *s,const int port)
wdenk78f66222002-08-27 10:27:51 +0000150{
151 while (*s) {
wdenk756f5862005-04-03 15:51:42 +0000152 _serial_putc (*s++,port);
wdenk78f66222002-08-27 10:27:51 +0000153 }
154}
155
156
157int
wdenk756f5862005-04-03 15:51:42 +0000158_serial_getc(const int port)
159{
160 return NS16550_getc(PORT);
161}
162
163int
164_serial_tstc(const int port)
165{
166 return NS16550_tstc(PORT);
167}
168
169void
170_serial_setbrg (const int port)
171{
172 int clock_divisor;
173
174 clock_divisor = calc_divisor(PORT);
175 NS16550_reinit(PORT, clock_divisor);
176}
177
178void
179serial_putc(const char c)
180{
181 _serial_putc(c,CONFIG_CONS_INDEX);
182}
183
184void
185serial_putc_raw(const char c)
186{
187 _serial_putc_raw(c,CONFIG_CONS_INDEX);
188}
189
190void
191serial_puts(const char *s)
192{
193 _serial_puts(s,CONFIG_CONS_INDEX);
194}
195
196int
wdenk78f66222002-08-27 10:27:51 +0000197serial_getc(void)
198{
wdenk756f5862005-04-03 15:51:42 +0000199 return _serial_getc(CONFIG_CONS_INDEX);
wdenk78f66222002-08-27 10:27:51 +0000200}
201
202int
203serial_tstc(void)
204{
wdenk756f5862005-04-03 15:51:42 +0000205 return _serial_tstc(CONFIG_CONS_INDEX);
wdenk78f66222002-08-27 10:27:51 +0000206}
207
208void
wdenk756f5862005-04-03 15:51:42 +0000209serial_setbrg(void)
wdenk78f66222002-08-27 10:27:51 +0000210{
wdenk756f5862005-04-03 15:51:42 +0000211 _serial_setbrg(CONFIG_CONS_INDEX);
wdenk78f66222002-08-27 10:27:51 +0000212}
213
214#endif