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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jorge Ramirez-Ortizd7542542017-06-26 15:52:49 +02002/*
3 * (C) Copyright 2017 Linaro
4 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Jorge Ramirez-Ortizd7542542017-06-26 15:52:49 +02005 */
6
Simon Glassf2176512020-02-03 07:36:17 -07007#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -07008#include <cpu_func.h>
Jorge Ramirez-Ortizd7542542017-06-26 15:52:49 +02009#include <dm.h>
Simon Glass9b4a2052019-12-28 10:45:05 -070010#include <init.h>
Simon Glass90526e92020-05-10 11:39:56 -060011#include <asm/cache.h>
Jorge Ramirez-Ortizd7542542017-06-26 15:52:49 +020012#include <asm/io.h>
13#include <dm/platform_data/serial_pl01x.h>
14#include <asm/arch/hi3798cv200.h>
Jorge Ramirez-Ortizd7542542017-06-26 15:52:49 +020015#include <asm/armv8/mmu.h>
Simon Glassc05ed002020-05-10 11:40:11 -060016#include <linux/delay.h>
Jorge Ramirez-Ortizd7542542017-06-26 15:52:49 +020017
18DECLARE_GLOBAL_DATA_PTR;
19
20static struct mm_region poplar_mem_map[] = {
21 {
22 .virt = 0x0UL,
23 .phys = 0x0UL,
24 .size = 0x80000000UL,
25 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
26 PTE_BLOCK_INNER_SHARE
27 }, {
28 .virt = 0x80000000UL,
29 .phys = 0x80000000UL,
30 .size = 0x80000000UL,
31 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
32 PTE_BLOCK_NON_SHARE |
33 PTE_BLOCK_PXN | PTE_BLOCK_UXN
34 }, {
35 0,
36 }
37};
38
39struct mm_region *mem_map = poplar_mem_map;
40
Shawn Guo655c6d92018-12-12 15:24:44 +080041#if !CONFIG_IS_ENABLED(OF_CONTROL)
Jorge Ramirez-Ortizd7542542017-06-26 15:52:49 +020042static const struct pl01x_serial_platdata serial_platdata = {
43 .base = REG_BASE_UART0,
44 .type = TYPE_PL010,
45 .clock = 75000000,
46};
47
48U_BOOT_DEVICE(poplar_serial) = {
49 .name = "serial_pl01x",
50 .platdata = &serial_platdata,
51};
Shawn Guo655c6d92018-12-12 15:24:44 +080052#endif
Jorge Ramirez-Ortizd7542542017-06-26 15:52:49 +020053
54int checkboard(void)
55{
56 puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
57
58 return 0;
59}
60
61void reset_cpu(ulong addr)
62{
63 psci_system_reset();
64}
65
66int dram_init(void)
67{
68 gd->ram_size = get_ram_size(NULL, 0x80000000);
69
70 return 0;
71}
72
73/*
74 * Some linux kernel versions don't use memory before its load address, so to
75 * be generic we just pretend it isn't there. In previous uboot versions we
76 * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
77 * could persist in memory and be left alone by the kernel.
78 *
79 * That led to a problem when mapping memory in older kernels. That PSCI code
80 * now lies in memory below the kernel load offset; it therefore won't be
81 * touched by the kernel, and by not specially reserving it we avoid the mapping
82 * problem as well.
83 *
84 */
85#define KERNEL_TEXT_OFFSET 0x00080000
86
87int dram_init_banksize(void)
88{
89 gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
90 gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
91
92 return 0;
93}
94
95static void usb2_phy_config(void)
96{
97 const u32 config[] = {
98 /* close EOP pre-emphasis. open data pre-emphasis */
99 0xa1001c,
100 /* Rcomp = 150mW, increase DC level */
101 0xa00607,
102 /* keep Rcomp working */
103 0xa10700,
104 /* Icomp = 212mW, increase current drive */
105 0xa00aab,
106 /* EMI fix: rx_active not stay 1 when error packets received */
107 0xa11140,
108 /* Comp mode select */
109 0xa11041,
110 /* adjust eye diagram */
111 0xa0098c,
112 /* adjust eye diagram */
113 0xa10a0a,
114 };
115 int i;
116
117 for (i = 0; i < ARRAY_SIZE(config); i++) {
118 writel(config[i], PERI_CTRL_USB0);
119 clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
120 udelay(20);
121 }
122}
123
124static void usb2_phy_init(void)
125{
126 /* reset usb2 controller bus/utmi/roothub */
127 setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
128 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
129 udelay(200);
130
131 /* reset usb2 phy por/utmi */
132 setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
133 udelay(200);
134
135 /* open usb2 ref clk */
136 setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
137 udelay(300);
138
139 /* cancel usb2 power on reset */
140 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
141 udelay(500);
142
143 usb2_phy_config();
144
145 /* cancel usb2 port reset, wait comp circuit stable */
146 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
147 mdelay(10);
148
149 /* open usb2 controller clk */
150 setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
151 USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
152 USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
153 udelay(200);
154
155 /* cancel usb2 control reset */
156 clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
157 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
158 udelay(200);
159}
160
Shawn Guoe7ab6df2018-12-18 17:52:06 +0800161#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
Simon Glass7b51b572019-08-01 09:46:52 -0600162#include <env.h>
Shawn Guoe7ab6df2018-12-18 17:52:06 +0800163#include <usb.h>
164#include <usb/dwc2_udc.h>
165#include <g_dnl.h>
166
167static struct dwc2_plat_otg_data poplar_otg_data = {
168 .regs_otg = HIOTG_BASE_ADDR
169};
170
171static void set_usb_to_device(void)
172{
173 setbits_le32(PERI_CTRL_USB3, USB2_2P_CHIPID);
174}
175
176int board_usb_init(int index, enum usb_init_type init)
177{
178 set_usb_to_device();
179 return dwc2_udc_probe(&poplar_otg_data);
180}
181
182int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
183{
184 if (!env_get("serial#"))
185 g_dnl_set_serialnumber("0123456789POPLAR");
186 return 0;
187}
188#endif
189
Jorge Ramirez-Ortizd7542542017-06-26 15:52:49 +0200190int board_init(void)
191{
192 usb2_phy_init();
193
194 return 0;
195}
196