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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Albert Aribaud39419ce2010-08-08 05:17:06 +05302/*
Albert ARIBAUD57b4bce2011-04-22 19:41:02 +02003 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert Aribaud39419ce2010-08-08 05:17:06 +05304 *
Albert ARIBAUD57b4bce2011-04-22 19:41:02 +02005 * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert Aribaud39419ce2010-08-08 05:17:06 +05306 */
7
8#include <common.h>
9#include <asm/io.h>
Simon Glassc05ed002020-05-10 11:40:11 -060010#include <linux/delay.h>
Albert Aribaud39419ce2010-08-08 05:17:06 +053011
Trevor Woernerb16a3312020-05-06 08:02:38 -040012#if defined(CONFIG_ARCH_ORION5X)
Albert Aribaud39419ce2010-08-08 05:17:06 +053013#include <asm/arch/orion5x.h>
Trevor Woernerbb0fb4c2020-05-06 08:02:40 -040014#elif defined(CONFIG_ARCH_KIRKWOOD)
Stefan Roese3dc23f72014-10-22 12:13:06 +020015#include <asm/arch/soc.h>
Stefan Roese81e33f42015-12-21 13:56:33 +010016#elif defined(CONFIG_ARCH_MVEBU)
Anton Schuberte863f7f2015-07-15 14:50:05 +020017#include <linux/mbus.h>
Albert Aribaud39419ce2010-08-08 05:17:06 +053018#endif
19
20/* SATA port registers */
21struct mvsata_port_registers {
Michael Walle70c55f52011-05-11 12:22:46 +000022 u32 reserved0[10];
23 u32 edma_cmd;
24 u32 reserved1[181];
Albert Aribaud39419ce2010-08-08 05:17:06 +053025 /* offset 0x300 : ATA Interface registers */
26 u32 sstatus;
27 u32 serror;
28 u32 scontrol;
29 u32 ltmode;
30 u32 phymode3;
31 u32 phymode4;
32 u32 reserved2[5];
33 u32 phymode1;
34 u32 phymode2;
35 u32 bist_cr;
36 u32 bist_dw1;
37 u32 bist_dw2;
38 u32 serrorintrmask;
39};
40
41/*
42 * Sanity checks:
43 * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
44 * - for ide_preinit to make sense, we need at least one of
Gray Remlinc08349e2013-02-06 10:59:38 +000045 * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET;
46 * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT.
Albert Aribaud39419ce2010-08-08 05:17:06 +053047 * Fail with an explanation message if these conditions are not met.
48 * This is particularly important for CONFIG_IDE_PREINIT, because
49 * its lack would not cause a build error.
50 */
51
52#if !defined(CONFIG_SYS_ATA_BASE_ADDR)
53#error CONFIG_SYS_ATA_BASE_ADDR must be defined
54#elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \
55 && !defined(CONFIG_SYS_ATA_IDE1_OFFSET)
56#error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \
57 must be defined
58#elif !defined(CONFIG_IDE_PREINIT)
59#error CONFIG_IDE_PREINIT must be defined
60#endif
61
62/*
63 * Masks and values for SControl DETection and Interface Power Management,
64 * and for SStatus DETection.
65 */
66
Michael Walle70c55f52011-05-11 12:22:46 +000067#define MVSATA_EDMA_CMD_ATA_RST 0x00000004
Albert Aribaud39419ce2010-08-08 05:17:06 +053068#define MVSATA_SCONTROL_DET_MASK 0x0000000F
69#define MVSATA_SCONTROL_DET_NONE 0x00000000
70#define MVSATA_SCONTROL_DET_INIT 0x00000001
71#define MVSATA_SCONTROL_IPM_MASK 0x00000F00
72#define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED 0x00000300
73#define MVSATA_SCONTROL_MASK \
74 (MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK)
75#define MVSATA_PORT_INIT \
76 (MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
77#define MVSATA_PORT_USE \
78 (MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
79#define MVSATA_SSTATUS_DET_MASK 0x0000000F
80#define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003
81
82/*
Albert Aribaudd3497132010-09-16 20:30:30 +053083 * Status codes to return to client callers. Currently, callers ignore
84 * exact value and only care for zero or nonzero, so no need to make this
85 * public, it is only #define'd for clarity.
Bin Menga1875592016-02-05 19:30:11 -080086 * If/when standard negative codes are implemented in U-Boot, then these
Albert Aribaudd3497132010-09-16 20:30:30 +053087 * #defines should be moved to, or replaced by ones from, the common list
88 * of status codes.
89 */
90
91#define MVSATA_STATUS_OK 0
92#define MVSATA_STATUS_TIMEOUT -1
93
94/*
Anton Schuberte863f7f2015-07-15 14:50:05 +020095 * Registers for SATA MBUS memory windows
96 */
97
98#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
99#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
100
101/*
102 * Initialize SATA memory windows for Armada XP
103 */
104
Stefan Roese81e33f42015-12-21 13:56:33 +0100105#ifdef CONFIG_ARCH_MVEBU
Anton Schuberte863f7f2015-07-15 14:50:05 +0200106static void mvsata_ide_conf_mbus_windows(void)
107{
108 const struct mbus_dram_target_info *dram;
109 int i;
110
111 dram = mvebu_mbus_dram_info();
112
113 /* Disable windows, Set Size/Base to 0 */
114 for (i = 0; i < 4; i++) {
115 writel(0, MVSATA_WIN_CONTROL(i));
116 writel(0, MVSATA_WIN_BASE(i));
117 }
118
119 for (i = 0; i < dram->num_cs; i++) {
120 const struct mbus_dram_window *cs = dram->cs + i;
121 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
122 (dram->mbus_dram_target_id << 4) | 1,
123 MVSATA_WIN_CONTROL(i));
124 writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
125 }
126}
127#endif
128
129/*
Albert Aribaud39419ce2010-08-08 05:17:06 +0530130 * Initialize one MVSATAHC port: set SControl's IPM to "always active"
131 * and DET to "reset", then wait for SStatus's DET to become "device and
132 * comm ok" (or time out after 50 us if no device), then set SControl's
133 * DET back to "no action".
134 */
135
Albert Aribaudd3497132010-09-16 20:30:30 +0530136static int mvsata_ide_initialize_port(struct mvsata_port_registers *port)
Albert Aribaud39419ce2010-08-08 05:17:06 +0530137{
138 u32 control;
139 u32 status;
Albert Aribaudd3497132010-09-16 20:30:30 +0530140 u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */
Albert Aribaud39419ce2010-08-08 05:17:06 +0530141
Michael Walle70c55f52011-05-11 12:22:46 +0000142 /* Hard reset */
143 writel(MVSATA_EDMA_CMD_ATA_RST, &port->edma_cmd);
144 udelay(25); /* taken from original marvell port */
145 writel(0, &port->edma_cmd);
146
Albert Aribaudd3497132010-09-16 20:30:30 +0530147 /* Set control IPM to 3 (no low power) and DET to 1 (initialize) */
Albert Aribaud39419ce2010-08-08 05:17:06 +0530148 control = readl(&port->scontrol);
149 control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
150 writel(control, &port->scontrol);
Albert Aribaudd3497132010-09-16 20:30:30 +0530151 /* Toggle control DET back to 0 (normal operation) */
152 control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
153 writel(control, &port->scontrol);
154 /* wait for status DET to become 3 (device and communication OK) */
155 while (--timeleft) {
Albert Aribaud39419ce2010-08-08 05:17:06 +0530156 status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
157 if (status == MVSATA_SSTATUS_DET_DEVCOMM)
158 break;
159 udelay(1);
160 }
Albert Aribaudd3497132010-09-16 20:30:30 +0530161 /* return success or time-out error depending on time left */
162 if (!timeleft)
163 return MVSATA_STATUS_TIMEOUT;
164 return MVSATA_STATUS_OK;
Albert Aribaud39419ce2010-08-08 05:17:06 +0530165}
166
167/*
168 * ide_preinit() will be called by ide_init in cmd_ide.c and will
169 * reset the MVSTATHC ports needed by the board.
170 */
171
172int ide_preinit(void)
173{
Simon Guinot2cb4fad2011-11-21 19:25:46 +0530174 int ret = MVSATA_STATUS_TIMEOUT;
Albert Aribaudd3497132010-09-16 20:30:30 +0530175 int status;
Simon Guinot2cb4fad2011-11-21 19:25:46 +0530176
Stefan Roese81e33f42015-12-21 13:56:33 +0100177#ifdef CONFIG_ARCH_MVEBU
Anton Schuberte863f7f2015-07-15 14:50:05 +0200178 mvsata_ide_conf_mbus_windows();
179#endif
180
Albert Aribaud39419ce2010-08-08 05:17:06 +0530181 /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
182#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
Albert Aribaudd3497132010-09-16 20:30:30 +0530183 status = mvsata_ide_initialize_port(
Albert Aribaud39419ce2010-08-08 05:17:06 +0530184 (struct mvsata_port_registers *)
185 (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
Simon Guinot2cb4fad2011-11-21 19:25:46 +0530186 if (status == MVSATA_STATUS_OK)
187 ret = MVSATA_STATUS_OK;
Albert Aribaud39419ce2010-08-08 05:17:06 +0530188#endif
189 /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
190#if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
Albert Aribaudd3497132010-09-16 20:30:30 +0530191 status = mvsata_ide_initialize_port(
Albert Aribaud39419ce2010-08-08 05:17:06 +0530192 (struct mvsata_port_registers *)
193 (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
Simon Guinot2cb4fad2011-11-21 19:25:46 +0530194 if (status == MVSATA_STATUS_OK)
195 ret = MVSATA_STATUS_OK;
Albert Aribaud39419ce2010-08-08 05:17:06 +0530196#endif
Simon Guinot2cb4fad2011-11-21 19:25:46 +0530197 /* Return success if at least one port initialization succeeded */
198 return ret;
Albert Aribaud39419ce2010-08-08 05:17:06 +0530199}