| Suman Anna | e18fb7d | 2019-09-04 16:01:35 +0530 | [diff] [blame] | 1 | TI K3 DSP devices |
| 2 | ================= |
| 3 | |
| 4 | The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems that |
| 5 | are used to offload some of the processor-intensive tasks or algorithms, for |
| 6 | achieving various system level goals. |
| 7 | |
| 8 | These processor sub-systems usually contain additional sub-modules like L1 |
| 9 | and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller, |
| 10 | a dedicated local power/sleep controller etc. The DSP processor cores in the |
| 11 | K3 SoCs is usually either a TMS320C66x CorePac processor or a TMS320C71x CorePac |
| 12 | processor. |
| 13 | |
| 14 | DSP Device Node: |
| 15 | ================ |
| 16 | Each DSP Core sub-system is represented as a single DT node. Each node has a |
| 17 | number of required or optional properties that enable the OS running on the |
| 18 | host processor (Arm CorePac) to perform the device management of the remote |
| 19 | processor and to communicate with the remote processor. |
| 20 | |
| 21 | Required properties: |
| 22 | -------------------- |
| 23 | The following are the mandatory properties: |
| 24 | |
| 25 | - compatible: Should be one of the following, |
| 26 | "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs |
| 27 | "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs |
| 28 | |
| 29 | - reg: Should contain an entry for each value in 'reg-names'. |
| 30 | Each entry should have the memory region's start address |
| 31 | and the size of the region, the representation matching |
| 32 | the parent node's '#address-cells' and '#size-cells' values. |
| 33 | |
| 34 | - reg-names: Should contain strings with the following names, each |
| 35 | representing a specific internal memory region (if |
| 36 | present), and should be defined in this order, |
| 37 | "l2sram", "l1pram", "l1dram" |
| 38 | NOTE: C71x DSPs do not have a "l1pram" memory. |
| 39 | |
| 40 | - ti,sci: Should be a phandle to the TI-SCI System Controller node |
| 41 | |
| 42 | - ti,sci-dev-id: Should contain the TI-SCI device id corresponding to the |
| 43 | DSP Core. Please refer to the corresponding System |
| 44 | Controller documentation for valid values for the DSP |
| 45 | cores. |
| 46 | |
| 47 | - ti,sci-proc-ids: Should contain 2 integer values. The first cell should |
| 48 | contain the TI-SCI processor id for the DSP core device |
| 49 | and the second cell should contain the TI-SCI host id to |
| 50 | which the processor control ownership should be |
| 51 | transferred to. |
| 52 | |
| 53 | - resets: Should contain the phandle to the reset controller node |
| 54 | managing the resets for this device, and a reset |
| 55 | specifier. Please refer to the following reset bindings |
| 56 | for the reset argument specifier, |
| 57 | Documentation/devicetree/bindings/reset/ti,sci-reset.txt |
| 58 | |
| 59 | Example: |
| 60 | --------- |
| 61 | |
| 62 | 1. J721E SoC |
| 63 | /* J721E remoteproc alias */ |
| 64 | aliases { |
| 65 | rproc6 = &c66_0; |
| 66 | rproc8 = &c71_0; |
| 67 | }; |
| 68 | |
| 69 | cbass_main: interconnect@100000 { |
| 70 | compatible = "simple-bus"; |
| 71 | #address-cells = <2>; |
| 72 | #size-cells = <2>; |
| 73 | ranges = <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */ |
| 74 | <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ |
| 75 | <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */ |
| 76 | |
| 77 | /* J721E C66_0 DSP node */ |
| 78 | c66_0: dsp@4d80800000 { |
| 79 | compatible = "ti,j721e-c66-dsp"; |
| 80 | reg = <0x4d 0x80800000 0x00 0x00048000>, |
| 81 | <0x4d 0x80e00000 0x00 0x00008000>, |
| 82 | <0x4d 0x80f00000 0x00 0x00008000>; |
| 83 | reg-names = "l2sram", "l1pram", "l1dram"; |
| 84 | ti,sci = <&dmsc>; |
| 85 | ti,sci-dev-id = <142>; |
| 86 | ti,sci-proc-ids = <0x03 0xFF>; |
| 87 | resets = <&k3_reset 142 1>; |
| 88 | }; |
| 89 | |
| 90 | /* J721E C71_0 DSP node */ |
| 91 | c71_0: dsp@64800000 { |
| 92 | compatible = "ti,j721e-c71-dsp"; |
| 93 | reg = <0x00 0x64800000 0x00 0x00080000>, |
| 94 | <0x00 0x64e00000 0x00 0x0000c000>; |
| 95 | reg-names = "l2sram", "l1dram"; |
| 96 | ti,sci = <&dmsc>; |
| 97 | ti,sci-dev-id = <15>; |
| 98 | ti,sci-proc-ids = <0x30 0xFF>; |
| 99 | resets = <&k3_reset 15 1>; |
| 100 | }; |
| 101 | }; |